Abstract: When etching is performed with respect to a silicon-containing material by using a dry etching apparatus having a dual power source, the application of bias power is initiated before oxidization proceeds at a surface of the silicon-containing material. Specifically, the application of the bias power is initiated before the application of source power is initiated. Alternatively, the source power and the bias power are applied such that the effective value of the source power reaches a second predetermined value after the effective value of the bias power reaches a first predetermined value.

Abstract: A method for producing a semiconductor structure including preparing a semiconductor substrate, and generating a lower first, a middle second and an upper third masking layer on a surface of the semiconductor substrate. The method further includes forming at least one first window in the upper third masking layer, structuring the middle second masking layer using the first window for transferring the first window, structuring the lower first masking layer using the first window for transferring the first window, and enlarging the first window to form a second window. The method for further includes restructuring the middle second masking layer using the second window for transferring the second window, structuring the semiconductor substrate, using the structured lower third masking layer, restructuring the lower first masking layer using the second window, and restructuring the semiconductor substrate using the restructured lower third masking layer.

Abstract: A method of manufacturing a semiconductor device comprising forming an insulating layer above a semiconductor layer, forming a conductive layer including at least tantalum and tantalum nitride, and etching the conductive layer with using a gas including SiCl4 and NF3.

Abstract: The present invention relates to plasma etching in which O2 gas is added with He gas as a main component. At an early stage of a plasma discharge, Cl2 gas is added and thereafter the supply of the Cl2 gas is stopped. A small amount of Cl2 gas is added in advance before the discharge start and thereafter the discharge is started.

Abstract: A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.

Abstract: A method for etching a metal layer is described. That method comprises forming a metal layer on a substrate, then exposing part of the metal layer to a wet etch chemistry that comprises an active ingredient with a diameter that exceeds the thickness of the metal layer.

Abstract: A semiconductor substrate is provided, on which there is arranged a first layer, a second layer and a third layer. The third layer is, for example, a resist mask that is used to pattern the second layer. The second layer is, for example, a patterned hard mask used to pattern the first layer. Then, the third layer is removed and a fourth layer is deposited. The fourth layer is, for example, an insulator that fills the trenches which have been formed in the first layer. Then, the fourth layer is planarized by a CMP step. The planarization is continued and the second layer, which is, for example, a hard mask, is removed from the first layer together with the fourth layer. The fourth layer remains in place in a trench which is arranged in the first layer.

Abstract: A ferroelectric capacitor in which damage caused by etching exposed faces of a ferroelectric layer of the capacitor is compensated by depositing a seeding layer of ferroelectric material such as PZT on one or more exposed faces of the ferroelectric layer and depositing an electrode layer made of conductive material such as platinum on the seeding layer. An oxygen annealing recovery process is applied to the device. The seeding layer can transform the phase of the damaged surfaces from amorphous to crystalline during the recovery annealing process and, at the same time, provide the damaged surfaces of the ferroelectric layer with missing element(s), for example lead. The oxygen necessary for recovery of the damage may be obtained through the platinum layer from the oxygen atmosphere.

Abstract: A method for optimizing a seasoning recipe for a dry etch process. The method includes setting a critical value of reproducibility, a main etch recipe, and a preliminary seasoning recipe. A test wafer is then etched using the preliminary seasoning recipe in a dry etch chamber. Next, a main etch process is performed with respect to at least 10 run wafers in the dry etch chamber using the main etch recipe and an end-point detection time for each wafer is determined. An initial dispersion and a standard deviation are then determined using the determined end-point detection times. The critical value of reproducibility is then compared to the initial dispersion. If the initial dispersion is equal to or less than the critical value of reproducibility, the preliminary seasoning recipe is used as the seasoning recipe, otherwise the preliminary seasoning recipe is modified and the process is repeated until an optimal seasoning recipe is determined.

Abstract: A method of manufacturing a microelectronics device including providing a substrate having an active layer, a dielectric layer and a structural layer, wherein the active layer is formed over the dielectric layer and the dielectric layer is formed over the structural layer. The method further includes forming an opening through the active layer thereby exposing a surface of the dielectric layer and defining active layer sidewalls. A spacer is formed covering a first portion of the exposed dielectric layer surface and substantially spanning one of the active layer sidewalls. At least a second portion of the exposed dielectric layer surface is then cleaned.

Abstract: A process is provided for etching a silicon based material in a substrate, such as a photomask, to form features with straight sidewalls, flat bottoms, and high profile angles between the sidewalls and bottom, and minimizing the formation of polymer deposits on the substrate. In the etching process, the substrate is positioned in a processing chamber, a processing gas comprising a fluorocarbon, which advantageously is a hydrogen free fluorocarbon, is introduced into the processing chamber, wherein the substrate is maintained at a reduced temperature, and the processing gas is excited into a plasma state at a reduced power level to etch the silicon based material of the substrate. The processing gas may further comprise an inert gas, such as argon.

Abstract: A method for plasma treatment etches an SiC layer with an increased etching rate and enhanced selectivities of SiC with respect to SiO2 and an organic layer. An etching gas is converted into plasma to etch SiC. The etching gas may include CHF3; CHF3 and N2, for example, a mixed gas of CHF3, N2 and Ar; or a material having C, H and F and a material having N but without any material having O.

Abstract: After forming a first insulating film of a silicon nitride film, a silicon nitrided oxide film or a silicon carbide film, a second insulating film of a silicon oxide film is formed on the first insulating film. In a chamber of a high density plasma etching system, the second insulating film is selectively etched by using a first etching gas including a fluorocarbon gas having a cyclic structure as a principal constituent, so as to form an upper hole in the second insulating film. Subsequently, in the same chamber, the first insulating film is selectively etched by using a second etching gas including an oxygen gas as a principal constituent, so as to form a lower hole continuous to the upper hole in the first insulating film.

Abstract: A system and a process for plasma etching a semiconductor device. The technique comprises periodically applying a heightened voltage bias during the plasma etching process so as to reduce accumulated charge on the surface of the semiconductor device during plasma etching of the device. In one embodiment, a heightened positive voltage and heightened negative voltage is applied to the semiconductor device while plasma etching is occurring to thereby induce charge to be removed from the semiconductor device.

Abstract: An improved method of patterning photoresist is described that is resistant to poisoning from nearby nitrogen containing layers. An inert resin is used to fill a via in a damascene stack. Then a second stack comprised of a barrier layer, a BARC, and a photoresist are formed on the damascene stack. The barrier layer is preferably an i-line or Deep UV photoresist comprising a polymer with hydroxy groups that can attract nitrogen containing compounds and prevent them from diffusing into the photoresist and causing scum during the patterning step. The photoresist pattern is etch transferred through underlying layers to form a trench in the damascene stack. Optionally, the resin is replaced by the barrier layer which fills the via and forms a planar layer on the damascene stack. The barrier layer is independent of exposure wavelength and can be readily implemented into manufacturing and is extendable to future technologies.

Abstract: A method for forming a fuse includes forming an interconnection pattern and a fuse pattern on a substrate using a damascene process. A passivation layer is formed on a surface of the substrate over the interconnection pattern and the fuse pattern. Then, the passivation layer is patterned to form a pad opening that exposes a portion of the interconnection pattern. A metal pad is formed on the interconnection pattern in the pad opening. A portion of the metal pad extends over the passivation layer. The passivation layer on the fuse pattern is partially etched to form a fuse opening.

Abstract: Novel aqueous, acid etch solutions comprising a fluorinated surfactant are provided. The etch solutions are used with a wide variety of substrates, for example, in the etching of silicon oxide-containing substrates.

Abstract: The invention provides a method for forming a bottle-shaped trench. A semiconductor substrate having a trench and a pad stack layer formed thereon is provided. A masking layer is then formed in the lower portion of the trench. Plasma nitridation is then performed to form a nitride layer covering the sidewalls of the trench, followed by removing the masking layer to expose the sidewalls of the trench. The lower portion of the trench is then expanded by etching to form a bottle-shaped trench.

Abstract: In accordance with a method of trench isolation, a first oxide layer is formed on a semiconductor substrate. A first conductive layer and a nitride layer are successively formed on the first oxide layer. The nitride layer, the first conductive layer and the first oxide layer are etched to form a nitride layer pattern, a first conductive layer pattern and an oxide layer pattern. A portion of the substrate adjacent to the first conductive layer pattern is etched to form a trench in the substrate. The trench is cured under dinitrogen monoxide (N2O) or nitrogen monoxide(NO) atmosphere. A second oxide layer is formed in the trench through an in-situ process.

Abstract: A semiconductor device including a bit line formed using a damascene technique and a method of fabricating the same. The method includes forming an insulating layer on a substrate, forming a groove by etching the insulating layer to a partial depth, and forming spacers on the inner walls of the groove. An opening is formed by etching the insulating layer disposed under the groove using the spacers as an etch mask. A conductive layer is formed to fill the opening. A capping layer is formed to fill the groove.