Abstract: A substrate having a copper wiring is prepared. An insulating film is formed on the copper wiring. The insulating film is etched with a gas containing fluorine to form an opening reaching the copper wiring. A plasma treatment is carried out on a surface of copper exposed at a bottom of the opening without turning plasma discharge off after forming the opening in the same chamber as the formation of the opening.

Abstract: Disclosed a method for dry etching a semiconductor wafer by a plasma generated between a power-supplied first electrode and a grounded second electrode. After the bottom surface of the edge of the wafer is in contact with the first electrode, and the top surface of the edge and the side surface of the wafer are etched by ionized plasma species generated by the plasma discharge of reactive ion etching. Then, after the upper surface of the edge of the wafer is in contact with the second electrode, and the bottom surface of the edge and the side surface of the wafer are etched by radicalized plasma species generated by the plasma discharge of plasma etching.

Abstract: A method used to fabricate a semiconductor device comprises etching a dielectric which results in an undesirable charge buildup along a sidewall formed in the dielectric during the etch. The charge buildup along a top and a bottom of the sidewall can reduce the etch rate thereby resulting in excessive etch times and undesirable etch opening profiles. To remove the charge, a sacrificial conductive layer is formed which electrically shorts the upper and lower portions of the sidewall and eliminates the charge. In another embodiment, a gas is used to remove the charge. After removing the charge, the dielectric etch may continue. Various embodiments of the inventive process and in-process structures are described.

Abstract: A slurry for use in polishing a first material having a first hardness, wherein the first material overlies a second material having a second hardness, and the second hardness is greater than the first hardness, includes an abrasive that has a hardness which is greater than that of the first material but less than that of the second material. In a particular embodiment of the present invention copper overlying a copper diffusion barrier is polished with a slurry having an abrasive which is harder than copper but less hard than the copper diffusion barrier. Iron oxide, strontium titanate, apatite, dioptase, iron, brass, fluorite, hydrated iron oxide, and azurite, are examples of materials that are harder than copper but less hard than materials typically used as copper diffusion barriers in integrated circuits.

Abstract: Using coated carbon black particles, coated with a selected coating material, as an abrasive in slurries or polishing pads for chemical-mechanical polishing processes. By adjusting the coating material on the carbon black particles, new abrasive particles for chemical-mechanical polishing are created with tailored performance properties.

Abstract: A method of forming shallow trench isolation includes etching trenches through a nitride layer, a polysilicon layer, and a pad oxide layer and into a semiconductor substrate. The trenches are filled with an oxide layer. A silicon oxynitride layer is deposited overlying the oxide layer and both these layers are polished away using a first slurry having high selectivity. A second polishing polishes away the oxide layer using a second slurry having a low selectivity. The nitride layer is removed and a third polishing is performed to planarize the oxide layer using a third slurry having high selectivity. Alternatively, the oxide layer is etched away except where it overlies the trenches. A first polishing is performed to polish away the oxide layer using a first slurry having a low selectivity. A second polishing is performed to polish away the oxide layer using a second slurry having high selectivity.

Abstract: Abstract of the Disclosure A method for manufacturing a semiconductor device including a conductive path extending from the upper surface of an insulating layer on a semiconductor substrate to a conductive member embedded in the insulating layer. An etching mask, which defines an etched hole for the conductor path, is formed on the insulating layer within a specified permissible error, and that portion of the insulating layer which is not covered by the etching mask is removed by a reactive ion etching unit having a reaction chamber into which a reactive gas of CHF3/CO is introduced at a CHF3/CO flow ratio of about 15/85. After this, the etched hole formed by an etching process is filled with a conductive material for the conductive path.

Abstract: A method of forming a via hole through a glass wafer includes depositing a material layer on an outer surface of the glass wafer, the material layer having a selection ratio higher than that of the glass wafer, forming a via-patterned portion on one side of the material layer, performing a first etching in which the via-patterned portion is etched to form a preliminary via hole, eliminating any remaining patterning material used in the formation of the via-patterned portion, performing a second etching in which the preliminary via hole is etched to form a via hole having a smooth surface and extending through the glass wafer, and eliminating the material layer. The method according to the present invention is able to form a via hole through a glass wafer without allowing formation of an undercut or minute cracks, thereby increasing the yield and reliability of MEMS elements.

Abstract: A method (10) for etching a through via (116, 118) on a wafer (100) of semiconductor material (102), wherein the wafer (100) has a front side surface (110) and a backside surface (106), is described. A layer of photoresist material (104) is applied to the backside surface (106). The layer of photoresist (104) is then exposed to a light source through a mask having a pre-selected pattern, wherein the developed photoresist is removed to form at least one via (112, 114) in the remaining photoresist layer (104). The remaining photoresist layer (104?) is then baked in order to form a hardened, remaining photoresist layer (104?). The semiconductor material 102 adjacent to the at least one via (112, 114) is then gas plasma etched to form a through via (116, 118) between the backside surface (106) and the front side surface (110).

Abstract: In a substrate treating unit, a removal liquid supplying mechanism supplies a removal liquid to the surface of a substrate. In order to retain the removal liquid on the surface of the substrate for a fixed time, a spin chuck is operated to spin the substrate at such a low speed as to retain the removal liquid on the substrate, or spins the substrate intermittently, or temporarily stops spinning of the substrate. Thus, treatment with the removal liquid progresses without a further supply of the removal liquid, thereby restraining consumption of the removal liquid.

Abstract: A process for removal of a photoresist mask used to etch openings in low k carbon-doped silicon oxide dielectric material of an integrated circuit structure, and for removing etch residues remaining from either the etching of the openings or removal of the resist mask, while inhibiting damage to the low k dielectric material comprises. The structure is exposed to a reducing plasma to remove a portion of the photoresist mask, and to remove a portion of the residues remaining from formation of the openings in the layer of low k dielectric material. The structure is then exposed to an oxidizing plasma to remove any remaining etch residues from the openings in the layer of low k dielectric material or removal of the resist mask.

Abstract: Method, materials and structures are described for the fabrication of dual damascene features in integrated circuits. In via-first dual damascene fabrication, a bottom-antireflective-coating (“BARC”) is commonly deposited into the via and field regions surrounding the via, 107. Subsequent trench etch with conventional etching chemistries typically results in isolated regions of BARC, 107a, surrounded by “fencing” material, 108, at the bottom of the via. Such fencing hinders conformal coating with barrier/adhesion layers and can reduce device yield. The present invention relates to the formation of a BARC plug, 107c, partially filling the via and having a convex upper surface, 400, prior to etching the trench. Such a BARC structure is shown to lead to etching without the formation of fencing and a clean dual damascene structure for subsequent coating.

Abstract: A method of fabricating an imprint stamp is disclosed. The imprint stamp includes a plurality of layers of material that are deposited in a deposition order. After deposition, each layer is patterned and then etched to form a portion of an application specific imprint pattern. The portion includes variations in a topography of the layer. The application specific imprint pattern comprises a plurality of features that are defined by the variations in the topographies of all of the layers of material that were deposited, patterned, and etched. The imprint stamp can be used in a soft-lithography process by pressing the application specific imprint pattern into a mask layer in which the application specific imprint pattern is replicated.

Abstract: A method of etching a dielectric layer formed on a substrate including a sequence of processing cycles, wherein each cycle comprises steps of depositing an inactive polymeric film, activating the film to etch the structure, and removing the film is disclosed. In one embodiment, the method uses a fluorocarbon gas to form the polymeric film and a substrate bias to activate such film.

Abstract: The present invention provides a method for manufacturing integrated-type photovoltaic devices wherein light is incident from a side opposite to its substrate. The advantage of the method is easy patterning. A first electrode film, a photoelectric conversion layer, and a second electrode film are laminated on an insulating layer of a substrate without separation to form a laminated film. A deep open groove is formed through the laminated film to the depth of the first electrode film so as to electrically separate the laminated film including the first electrode film. Two shallow open grooves are formed parallel with, but slightly away from the deep open groove, and separate the laminated film upto the second electrode film. The second electrode film having three or more open grooves are used as a mask to remove the photoelectric conversion layer by etching to expose the first electrode film at bottoms of at least one shallow open groove.

Abstract: An STI structure and fabricating method thereof are disclosed. The STI fabricating method comprises forming a pad oxide layer and a first nitride layer on a substrate. A trench is formed by etching the first nitride layer, the pad oxide layer and the substrate. An oxide and a second nitride layer are deposited on the surface of the substrate including the trench. A spacer is formed on the lateral walls of the trench by etching the second nitride layer. A buried oxide is grown in the substrate underneath the trench by performing thermal oxidation on the substrate. The trench is then filled by depositing an insulating layer after removing the spacer and performing a planarization process. The STI fabricating method can reduce substantially a total parasitic capacitance. Therefore, gate RC delay is reduced and the operating speed of a transistor increases.

Abstract: A method for forming a SiGe HBT, which combines a SEG and Non-SEG growth, is disclosed. The SiGe base layer is deposited by a Non-SEG method. Then, the first-emitter layer is developed directly upon the SiGe base layer that has a good interface quality between the base-emitter. Next, a second poly silicon layer, which has a dopant concentration range within 1E19 to 1E21 (atom/cc), is deposited by SEG method. It not only reduces the resistance of the SiGe base layer, but also avoids the annealing that may influence the performance of the device.

Abstract: A method for manufacturing a semiconductor device that comprises defining a semiconductor substrate, forming a gate oxide on the semiconductor substrate, forming a polycrystalline silicon layer over the gate oxide, forming a tungsten silicide layer over the polycrystalline silicon layer; providing a mask over the tungsten silicide layer, defining the mask to expose at least one portion of the tungsten silicide layer, etching the exposed tungsten silicide layer with a first etchant, wherein some tungsten silicide layer remains, etching the remaining tungsten silicide layer with a second etchant to expose at least one portion of the polycrystalline silicon layer, annealing the tungsten silicide layer, etching the exposed polycrystalline silicon layer, and oxidizing sidewalls of the tungsten silicide layer and the polycrystalline silicon layer.

Abstract: A plasma processing method for etching a sample having a gate oxide film which generates a plasma in a vacuum chamber using electromagnetic waves, applies an rf bias power to the sample, turns off the rf bias power before a charged voltage of the sample reaches a breakdown voltage of the gate oxide film, turns on the rf bias power after the charged voltage of the sample has substantially dropped and repeats the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time, and the plasma is generated by continuously supplying power to enable generation of the plasma during the repeated turning on and off of the rf bias power.

Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and modifying a first portion of the high-k gate dielectric layer to ensure that it may be removed selectively to a second portion of the high-k gate dielectric layer.