Abstract: The multiprocessor system includes one or a plurality of main processors and a plurality of sub-processors, and an execution control circuit which conducts execution control of each the sub-processors, wherein the execution control circuit includes an execution control processor for execution control processing of each the sub-processors, a control bus output unit for activation of a command to each the sub-processors, a status bus input unit for status notification from each the sub-processors, a determination circuit which determines whether or not the status notification has one-to-one dependency with a processing command to be issued next on an operation sequence and is to be processed at a high speed, a status accelerator which issues a corresponding processing activation command when the status notification is to be processed at a high speed, and a status FIFO control unit which processes the status notification by using the execution control processor.

Abstract: A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss.

Abstract: A technique for restoring a register renaming map is described. In one example, a restore table having a number of storage locations saves a copy of the register renaming map whenever a flow-risk instruction is passed to a re-order buffer. When all storage locations are full, further instructions still pass to the re-order buffer, but a copy of the map is not saved. A storage location subsequently becomes available when its associated flow-risk instruction is executed. A register renaming map state for an unrecorded flow-risk instruction passed to the re-order buffer while the storage locations were full is generated and stored in the available location. This is generated using the restore table entry for a previous flow-risk instruction and re-order buffer values for intervening instructions between the previous and unrecorded flow-risk instructions. The restore table can be used to restore the map if an unexpected change in instruction flow occurs.

Abstract: A receptacle connector for a electronic device includes two sets of contacts arranged in two opposing rows in a cavity. A corresponding plug connector can be inserted into the receptacle connector so as to contact both sets of contacts. The receptacle connectors includes contacts that are dedicated for DisplayPort signals and contacts that provide non-DisplayPort signals. The contacts dedicated for DisplayPort signals are only enabled if the electronic device receives a notification from a connected accessory that that the accessory supports DisplayPort capability. Otherwise these contacts are in an “open” or deactivated state.

Abstract: The present invention discloses a method for locating the reference frames of the reference lane on the transmitting data bus. The present invention addresses this object by disclosing a method whereby the relationship between the size of the reference frame transmitted over the reference lane and the width of the data bus is such that the reference frame is bit-shifted automatically until it is aligned with the data bus.

Abstract: Aspects of the present disclosure describe automatically changing an output mode of an output device from a first output mode to a latency reduction mode. An initiation signal and the output data may be received from a client device platform or a signal distributor. Upon receiving the initiation signal, the output device may change the output mode from the first output mode to the latency reduction mode. Thereafter, the output device may receive an end latency reduction mode signal. The output device may then revert back to the first output mode. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: An integrated interface system for a power-system monitoring and control system is provided. The integrated interface system includes an input and output (I/O) interface unit 220 performing data transmission to and reception from the external data source system; and a data exchange unit exchanging data by using the naming of a fixed electrical bus number for data exchange between a power-system monitoring and control system and the external data source system having a DB different from the power-system monitoring and control system.

Abstract: A system and methods for sending data from one process to another process (i.e., interprocess communication) are disclosed. In accordance with one embodiment, an operating system recognizes a request by a sending process to perform an asynchronous write to a pipe, and a request by a receiving process to perform an asynchronous read from the pipe, occurring in either order. The operating system then selects one of a plurality of mechanisms for providing the data to the receiving process.

Abstract: One embodiment relates to an integrated circuit with a modular direct memory access system. A read data mover receives data obtained from a source address, and a write data mover for sends the data to a destination address. A descriptor controller provides the source address to the read data mover and the destination address to the write data mover. Another embodiment relates to a method of providing direct memory access. Another embodiment relates to a system which provides direct memory access. Other embodiments and features are also disclosed.

Abstract: Embodiments relate to message-based installation management using a message bus. In embodiments, a deployment server or other provisioning host can be connected to a resource via a message bus. A processor monitors the bus message traffic to detect a message activity. The processor generates an installation command to cause a software installation in a managed network in view of the message activity detected on the message bus.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable multipass programming in buffers implemented in non-volatile data storage systems (e.g., using one or more flash memory devices). In one aspect, a portion of memory (e.g., a page in a block of a flash memory device) may be programmed many (e.g., 1000) times before an erase is required. Some embodiments include systems, methods and/or devices to integrate Bloom filter functionality in a non-volatile data storage system, where a portion of memory storing one or more bits of a Bloom filter array may be programmed many (e.g., 1000) times before the contents of the portion of memory need to be moved to an unused location in the memory.

Abstract: A game apparatus as an information processing apparatus includes a CPU, and the CPU generates data for generation from information specific to the game apparatus and random numbers, and calculates hash value data by using the data for generation. On the other hand, the CPU extracts the apparatus-specific information from the taken data for generation, and determines whether it is correct or not. In a case that it is determined that the apparatus-specific information is correct, hash value data is calculated by using the taken data for generation. Then, the CPU executes game processing regarding the hash value data as a parameter in a case that the taken hash value data and the calculated hash value data are coincident with each other. In a case that the apparatus-specific information is not correct or in a case that the two hash value data is not coincident with each other, the communication game is not started.

Abstract: Systems and methods are described including dynamically configuring a shared buffer to support processing of at least two video read streams associated with different video codec formats. The methods may include determining a buffer write address within the shared buffer in response to a memory request associated with one read stream, and determining a different buffer write address within the shared buffer in response to a memory request associated with the other read stream.

Abstract: An apparatus comprises a cable including conductors to carry data signals and a power voltage from a device when the cable is connected to the device, and at least one active display assembly fixed along a length of the cable. The active display assembly includes a power converter connected to the conductors to convert the power voltage to a supply voltage, and a programmable display and a controller powered by the power converter. The programmable display is configured to display programmed indicia responsive to the supply voltage, and the controller is configured to program the display.

Abstract: A Data Throttling method duplicates the full-speed transmission of data so that it appears to be transmitting at a 10 Mhz rate. Additional storage elements and multiplexers are added along the data path but this completely eliminates undesirable complexity in the clock tree. In a two-bit application, data is received and transmitted two bits at a time, and yet the output 10 Mhz data rate is maintained. For an even ratio between the system clock rate and the 10 Mhz clock signal rate, bit0 is transmitted for half the time and bit1 is transmitted for the other half of the time. But if the full-speed clock rate is an odd multiple of 10 Mhz, then there will be a “split cycle” including one bit0 and one bit1.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a plurality of solid-state non-volatile memory cells. A controller communicates a first command having address information and a first operation code. The first operation code identifies a first action to be taken by the memory module in relation to the address information. The controller subsequently communicates a second command having a second operation code without corresponding address information. The memory module takes a second action identified by the second command using the address information from the first command.

Abstract: A system and method for discovering multiple paths to a disk device are disclosed. For example, the method can include discovering a plurality of paths that exist from a first host computer to a storage device. The plurality of paths includes at least one local path and at least one network path from the first host computer to the storage device. In addition, the first host computer is one of several host computers in a cluster. Once the paths have been discovered, a representation of the paths from the first host computer to the storage device is generated. Such a method can be performed, for example, without user intervention.

Abstract: A volatile memory device includes a memory cell array, a command decoder, a self-refresh circuit, and a register. The command decoder is configured to decode a self-refresh entry command, a self-refresh exit command, and a register read command based on external command signals received from outside the volatile memory device. The self-refresh circuit is configured to automatically refresh the memory cell array during a self-refresh mode which be entered in response to the self-refresh entry command and be exited in response to the self-refresh exit command. The register is configured to store an accessible state in response to the self-refresh exit command, and output the stored accessible state in response to the register read command. The accessible state indicates whether or not the memory cell array is ready to be read or written.

Abstract: The invention is a method of programming a device comprising a USB® connector and a USB® chip. The USB® connector comprises first and second sets of connection pins. The USB® chip comprises a USB® interface and a programming interface. The method comprises a step of activating a selecting pin of said first set for selecting the programming interface and a step of sending programming data to the USB® chip through said second set and through the programming interface.

Abstract: A system for processing interrupts in a virtualized computing environment includes a virtual interrupt controller to provide virtual interrupts from peripherals to virtual machines. The system also includes a virtual interrupt filter that has an estimator circuit to provide an estimate of what proportion of interrupts from one or more of the peripherals are virtual interrupts. A determination is made as to whether the estimate satisfies a criterion; if it does, incoming interrupts are blocked.