Abstract: The present application relates to methods and systems for intelligently routing requests to one of a plurality of redundant servers. The methods and systems route the requests to a most highly ranked redundant server. The redundant servers are dynamically rank according to ranking information, wherein the ranking information may include server performance information, server response information, next step performance information, next step response information, historic information and other like information. Next step response information and next step performance information corresponds to information pertaining to servers the plurality of redundant servers depend upon. The methods and systems may further randomly re-rank the plurality of redundant servers. The methods and systems may further re-route unprocessed requests meeting non-performance criteria.

Abstract: A data transfer operation completion detection circuit including a first counter for performing a shifting operation in response to the generation of a read initiation signal, a second counter for performing a shifting operation in response to the generation of a burst completion signal, and an SR latch circuit for generating a read enable signal in response to the burst completion signal being generated when the count value of the first counter matches the count value of the second counter. The completion of a read operation or another data transfer operation is thus detected based on a read initiation signal reception history; therefore, it is possible to detect whether all read operations are complete at a given time even if a new read command is received while a read operation or the like is in progress.

Abstract: Provided are a method for selecting a path comprising ports on primary and secondary clusters to use to transmit data at a primary volume to a secondary volume. A request is received to copy data from a primary storage location to a secondary storage location. A determination is made from a plurality of primary clusters of an owner primary cluster for the primary storage location, wherein the primary clusters are configured to access the primary storage location. A determination is made as to whether there is at least one port on the owner primary cluster providing an available path to the secondary storage location. One port on the owner primary cluster is selected to use to copy the data to the secondary storage location in response to determining that there is at least one port on the owner primary cluster available to transmit to the secondary storage location.

Abstract: Described are systems and methods for instrumenting configuration and system settings based on targeting configuration settings at dynamically populated groups, groups with varied membership, and objects defined in a class. The systems and methods provide for attributing a configuration setting or policy to one or more objects and then targeting the object at one or more scopes.

Abstract: A data transfer operation completion detection circuit including a first counter for performing a shifting operation in response to the generation of a read initiation signal, a second counter for performing a shifting operation in response to the generation of a burst completion signal, and an SR latch circuit for generating a read enable signal in response to the burst completion signal being generated when the count value of the first counter matches the count value of the second counter. The completion of a read operation or another data transfer operation is thus detected based on a read initiation signal reception history; therefore, it is possible to detect whether all read operations are complete at a given time even if a new read command is received while a read operation or the like is in progress.

Abstract: Method, circuit, and system for performing an operation for regulating bandwidth, the operation comprising receiving at a memory, debug data packets and functional data packets for transmittal on a shared bus. The operation then transmits, via the shared bus, the functional data packets and one or more of the debug data packets according to a predefined ratio of debug data packets to functional data packets. The operation then drops one or more of the received debug data packets at the memory, and maintains a count of the one or more dropped debug data packets. The operation then updates the predefined ratio based on the count, and uses the updated predefined ratio to transmit the functional data packets and one or more of the debug data packets.

Abstract: A method of initializing programmable devices on a shared bus, comprises, on power up, loading control instructions on a processor from an attached tangible, non-transient computer-readable medium, automatically allowing a first programmable device on a common bus to exit its reset state and enter a read-to-program state as the computer system powers up, automatically holding a second programmable device on the common bus in its reset state, querying the common bus by the processor to identify the first programmable device, copying the contents of a program image file by the processor from the computer-readable medium across the common bus to the first programmable device, and once the first programmable device has been programmed with the contents of the program image file, signaling the first programmable device to release the reset hold on the second programmable device.

Abstract: In a storage system which includes a plurality of microprocessors, it is desired to prevent delay in I/O responses due to synchronous processing waiting for asynchronous processing, while still ensuring the throughput of asynchronous processing. In a plurality of microprocessors possessed by a controller, synchronous processors and asynchronous processors are mixed together. The synchronous processors are microprocessors whose duty is to perform synchronous processing and not to perform asynchronous processing. And the asynchronous processors are microprocessors whose duty is to perform asynchronous processing and not to perform synchronous processing.

Abstract: A system and method for transporting the look, feel, and function of one's personalized computer preferences across multiple host computers, including the appearance, settings, programs, and user data. This system and method uses a portable memory device and a data management system that maintains a consistent interface and data file structure on multiple host computers, including a common visual desktop interface. The portable memory solution also provides mobile access to the user's applications and personal data files. The memory device is capable of being connected to multiple host computers via a standard interface such as a USB port.

Abstract: A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID accompanying the fed DT for another device and the fed ID is latched in a register of the device. In a case of no-match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection.

Abstract: In a wizard process used by a printer driver, a screen to be displayed is dynamically produced in accordance with device function information provided by the printer driver and a setting value input by a user. In this technique, it is not necessary to separately prepare wizard programs for respective printer drivers, which makes it possible to develop the wizard program in a highly efficient and easy manner.

Abstract: A method of controlling one or more devices in data communication with a common controller to perform one or more functions, each of the devices having a synchronous clock, a synchronized real time clock register and a memory, the method comprising: arming the devices such that the devices commence performing the functions synchronously, receive and store to their respective memory data acquired as a result of performing the functions and store to their respective memory time stamp information indicative of the time of acquisition of the acquired data; a trigger device in data communication with the common controller responding to a command to perform the functions by sending a first message to the host controller that includes data indicative of a time of receipt of the command; the host controller responding to the first message by sending the devices a second message including data indicative of the time of receipt by the further device of the command; and the devices responding to the second message by re

Abstract: A host-peripheral adaptor includes a host adaptor and a portable peripheral adaptor. The host adaptor includes a substantially flat peripheral-adaptor-side interface. The peripheral-adaptor-side interface is designed in a way that it is not easy to tamper with. The portable peripheral adaptor includes a host-adaptor-side interface that is designed to operatively connect to the peripheral-adaptor-side interface of the host adaptor. The portable peripheral adaptor also includes one or more peripheral-side interfaces for accommodating one or more peripheral devices such as a storage media. The portable peripheral adaptor and the host adaptor include a set of data lines and the host adaptor also includes circuitry for recognizing the specific type of a peripheral device and, based on its specific type, for setting a suitable communication path to transfer data between a host and the peripheral device.

Abstract: A power control device coupled to a power supply device and an information processing device, and configured to control a power supply from the power supply device to the information processing device, the power control device including: a first input/output unit configured to input/output data from/to the information processing device; a second input/output unit configured to input/output data from/to the power supply device by a change of state of signal lines; a storage unit configured to store data input from the first input/output unit and the second input/output unit; and a control unit configured to execute a conversion process for converting data input from the first input/output unit to a change of state of a signal line that can be output from the second input/output unit, and converting a change of state of a signal line input from the second input/output unit to a data format that can be output from the first input/output unit.

Abstract: A nondestructive testing apparatus includes a storage section which stores a plurality of predetermined functions which are executable by the nondestructive testing apparatus, each of the predetermined functions being initially set to one of a permitted state and a disabled state; an input section which includes a plurality of input portions respectively corresponding to the predetermined functions; and a control section which is adapted to receive permission information including information which unlocks at least one of the predetermined functions initially set in the disabled state so as to be set to the permitted state. The control section automatically assigns the at least one predetermined function which has been unlocked to the corresponding input portion of the input section.

Abstract: The disclosure provides an HVAC data processing and communication network and a method of manufacturing the same. In an embodiment, the method includes configuring a subnet controller. The subnet controller is configured to assign to a first device associated with the network a first equipment type number based on a first device ID number and a first offset. The subnet controller is configured, in the event that the first device shares a same enclosure with a second device associated with the network, to assign to the second device a second equipment type number based on the first device ID number and a second offset. The subnet controller is configured, in the event that the first device does not share a same enclosure with the second device, to assign to the second device the second equipment type number based on a second device ID number and the second offset.

Abstract: A memory/storage module is provided that implements a solid state drive compatible with Serial Advanced Technology Attachment (SATA) or Serial Attached SCSI (SAS) signaling on a double-data-rate compatible socket. A detachable daughter card may be coupled to the memory module for converting a memory bus voltage to a second voltage for memory devices on the memory module. Additionally, a hybrid memory bus on a host system is provided that supports either DDR-compatible memory modules and/or SATA/SAS-compatible memory modules. In one example, the memory/storage module couples to a first bus (DDR3 compatible socket) to obtain voltage and/or other signals, but uses a second bus for data transfers. In another example, the memory module may repurpose/reuse electrical paths that typically carry non-data signals for data traffic to/from the memory/storage module. Such data traffic for the memory/storage module permits concurrent data traffic for other memory modules on the same memory bus.

Abstract: A method for operating a KVM switch with independent OSD and control channels comprises the steps of: receiving a functional instruction from the operation and control device; outputting a switch signal to turn off the picture of the selected computer, and starting the channel for the OSD signals; retrieving a pre-stored OSD background picture, and outputting the OSD background video signal and the control command to the OSD processing chip and OSD video switching circuit, and displaying via the monitor; inputting a functional instruction to select an OSD operation picture; outputting the selected OSD operating picture to the OSD processing chip and then to the monitor; inputting a functional instruction to stop the OSD operation; the OSD control system unit enabling the OSD video switching circuit to turn off the channel of the OSD signals, and controlling to switch back to the picture of the computer.

Abstract: Techniques are disclosed for managing the flow of IO jobs from a client to a hardware device such that resource starvation is reduced without significantly impacting throughput. Each flow can be assigned an amount of time that a hardware device can deplete completing IO jobs from the client. When the allocated amount of time is used IO jobs associated with the client can be stored in a queue until the client obtains more time.

Abstract: The present invention discloses a method for locating the reference frames of the reference lane on the transmitting data bus. The present invention addresses this object by disclosing a method whereby the relationship between the size of the reference frame transmitted over the reference lane and the width of the data bus is such that the reference frame is bit-shifted automatically until it is aligned with the data bus.