Patents Examined by Kris Rhu
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Patent number: 8914558Abstract: The storage unit of a peripheral device has a first storage area and a second storage area. The first storage area stores a plurality of control programs corresponding to a plurality of operating systems of different types. The second storage area is a storage area which is recognized by an information processing apparatus as an external storage device and in which at least one control program is replicated from the first storage area. The information processing apparatus reads out the control program from the second storage recognized by it as the external storage device, and executes the program. The information processing apparatus thus controls the peripheral device.Type: GrantFiled: October 24, 2012Date of Patent: December 16, 2014Assignee: Canon Denshi Kabushiki KaishaInventors: Kiyoshi Ito, Hirokazu Higuchi, Ayaka Sato, Yuuki Taguchi
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Patent number: 8909829Abstract: Methods and apparatus to create a volume using an automated storage tier policy and a virtual storage tier from storage pools having a plurality of disk types. In one embodiment, a utilization percentage for the storage virtual tiers is used.Type: GrantFiled: September 26, 2013Date of Patent: December 9, 2014Assignee: EMC CorporationInventors: Stalinsaravanakumar Thangapalam, Anoop George Ninan, Katakam Gangadhar
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Patent number: 8880740Abstract: Embodiments of the present invention address deficiencies of the art in respect to computing device location and provide a novel and non-obvious method, system and computer program product for visually locating a computing device. In one embodiment of the invention, a computing device location method can include establishing filter criteria grouping different computing devices by common characteristic, wirelessly broadcasting the filter criteria in a discovery request to in range peripheral locators coupled to computing devices, aggregating a list of discovered peripheral locators meeting the filter criteria, selecting at least one of the peripheral locators in the list, and interrogating the selected peripheral locators to retrieve data provided by corresponding ones of the computing devices. Additionally, a display element in each of the discovered peripheral locators can be illuminated upon discovering the peripheral locators.Type: GrantFiled: October 24, 2007Date of Patent: November 4, 2014Assignee: International Business Machines CorporationInventors: Selcuk S. Eren, Brian J. Jaeger, Douglas A. Law, Paul A. Roberts, Shawn K. Sremaniak
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Patent number: 8880759Abstract: An apparatus includes first, second, and spare ports, where first data having a data length less than a predetermined value is transmitted from the first port and second data having a data length not less than the predetermined value is transmitted from the second port. The apparatus obtains a first determination result indicating whether input data is the first data or the second data and a second determination result indicating whether a transmission rate of each of the first and second ports is equal to or greater than a threshold. The apparatus sorts the input data to one of the first, second, and spare ports, based on the first and second determination results. The apparatus fragments the second data and transmit the fragmented second data to the spare port when both the first data and the second data are sorted to the spare port.Type: GrantFiled: March 8, 2013Date of Patent: November 4, 2014Assignee: Fujitsu LimitedInventors: Takuya Maeda, Tetuya Yokoyama
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Patent number: 8874805Abstract: A mechanism is provided for offloading an input/output (I/O) completion operation. Responsive to a second processor identifying that a flag has been set by a first processor requesting assistance in completing an I/O operation, the second processor copies an I/O response from a first I/O response data structure associated with the first processor to a second I/O response data structure associated with the second processor. The second processor deletes the I/O response from the first I/O response data structure, clears the flag, and processes the I/O operation by addressing the I/O response in the second I/O response data structure. Responsive to completing the I/O operation, the second processor deletes the I/O response from the second I/O response data structure.Type: GrantFiled: November 19, 2012Date of Patent: October 28, 2014Assignee: International Business Machines CorporationInventors: Bruce G. Mealey, Greg R. Mewhinney, Mysore S. Srinivas, Suresh E. Warrier
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Patent number: 8850088Abstract: A computer system includes a server using a virtual volume (virtual logical volume) shared by a plurality of storage apparatuses. A management system managing the computer system accepts a selection of a first storage apparatus to be a determination target from among the storage apparatuses, performs a first determination of whether a first access path including the first storage apparatus exists or not. If the first access path exists, the management system performs a second determination of whether or not the first access path is an active access path used by the server for accessing the storage area (the storage area of the storage apparatus) assigned to a part of the virtual volume used by the server, and determines whether the first storage apparatus can be stopped or not on the basis of a result of the first determination or a result of the second determination. The access path is a path from the server to one of the storage apparatuses.Type: GrantFiled: April 18, 2012Date of Patent: September 30, 2014Assignee: Hitachi, Ltd.Inventors: Yuuki Miyamoto, Katsutoshi Asaki
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Patent number: 8850404Abstract: A relational model may be used to encode primitives for each of a plurality of threads in a multi-core processor. The primitives may include tasks and parameters, such as buffers. Implicitly created tasks, like set render target, may be visualized by associating those implicitly created tasks with actual coded tasks.Type: GrantFiled: December 23, 2009Date of Patent: September 30, 2014Assignee: Intel CorporationInventors: Christopher J. Cormack, Nathaniel Duca, Mike Burrows, Serhat A. Tekin
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Patent number: 8843668Abstract: To add an unpackaged interface without adding a new connector to an information processing device. An information processing device includes: a first control device connected, when first equipment is attached, to the equipment via a terminal train containing a first detection terminal; a second control device; and a connection control device detecting, when the second equipment is attached, a detection signal of the second equipment via the first detection terminal and connecting the second equipment to the second control device based on the detection signal.Type: GrantFiled: February 27, 2012Date of Patent: September 23, 2014Assignee: Fujitsu LimitedInventors: Hirotaka Yakame, Akira Morita
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Patent number: 8843671Abstract: Various embodiments of the invention provide resource management of available data bandwidth of a SAS system in a non-uniform way. In certain embodiments, arbitration wait time values are adaptively modified to achieve a specified performance quota for a link.Type: GrantFiled: February 27, 2012Date of Patent: September 23, 2014Assignee: PMC-Sierra US Inc.Inventors: Gregory Arthur Tabor, Kurt Marshall Schwemmer, John Matthew Adams
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Patent number: 8838850Abstract: A cluster of storage control members connect different clients to different storage disks. Connection path information between the different clients and disks is discovered and distributed to the storage cluster members. The connection path information is then used to maintain coherency between tiering media contained in the different storage cluster members. Unique Small Computer System Interface (SCSI) identifiers may be associated with the different connection paths to uniquely identify particular storage disks connected to the clients.Type: GrantFiled: November 16, 2009Date of Patent: September 16, 2014Assignee: Violin Memory, Inc.Inventors: Sivaram Dommeti, Som Sikdar, Erik de la Iglesia
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Patent number: 8825909Abstract: An application directed method for substituting a driver for a target device includes the steps of updating a set of hardware identifiers for the target device to include a new hardware device, building a list of drivers based on the set of hardware identifiers that includes the new hardware identifier, and calling into an operating system to cause the operating system to switch the driver for the target device to a new driver which is selected from the list. With this method, a device that has multiple drivers associated therewith can have just one of the drivers substituted, and where multiple devices share the same hardware ID, the driver for just one of the devices can be substituted.Type: GrantFiled: February 28, 2011Date of Patent: September 2, 2014Assignee: VMware, Inc.Inventor: Matthew Ray Delco
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Patent number: 8806078Abstract: In an information processing device according to an embodiment, a generating unit generates a descriptor including information indicating an area in a storage unit and state information indicating a state of an entry in which the information indicating the area is stored, and an update unit updates the state information according to at least one of writing and reading of data to the area indicated in the entry selected according to the state information by the input/output unit. The generating unit generates the descriptor in advance before at least one of writing and reading of data to/from the storage unit is started.Type: GrantFiled: February 27, 2012Date of Patent: August 12, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Nobuhiko Sugasawa, Masataka Goto, Yuta Kobayashi, Shinichi Baba
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Patent number: 8806073Abstract: A content-aware digital media storage device includes a host device interface for exchanging digital information with a host device, a memory array for storing digital information received from the host device via the host interface, a peripheral module configured to communicate the digital information stored in the memory array to a receiver located remote from the digital media storage device, and a controller communicatively coupled to the host device interface, the memory array and the peripheral module configured to interpret directory information associated with the digital information stored in the memory array so as to selectively access said digital information and communicate such accessed digital information to the peripheral module for transmission to the remote receiver. Digital images stored in the memory array may be transmitted to a remote host via a wireless network access point with which the peripheral module of the storage device is associated.Type: GrantFiled: November 20, 2012Date of Patent: August 12, 2014Assignee: Eye-Fi, Inc.Inventors: Eugene Feinberg, Yuval Koren, Berend Ozceri
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Patent number: 8806082Abstract: A Direct Memory Access (DMA) device for a multi-core system, and an operating method of the DMA device are provided. The DMA device includes a channel state determining unit to determine whether at least one channel among a source channel and a destination channel is available, the source channel being formed between a source core and the DMA device, and the destination channel being formed between a destination core and the DMA device, and a data transmission processing unit to process data of the source core to be transmitted to the destination core, when both the source channel and the destination channel are determined to be available.Type: GrantFiled: July 29, 2011Date of Patent: August 12, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Doo Hyun Kim
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Patent number: 8806067Abstract: Systems and methods for configuring contacts of a first connector includes detecting mating of a second connector with the first connector and in response to the detection, sending a command over one of the contacts and waiting for a response to the command. If a valid response to the command is received, the system determines the orientation of the second connector. The response also includes configuration information for contacts in the second connector. The system then configures some of the other contacts of the first connector based on the determined orientation and configuration information of the contacts of the second connector.Type: GrantFiled: November 16, 2012Date of Patent: August 12, 2014Assignee: Apple Inc.Inventors: Jeffrey J. Terlizzi, Scott Mullins, Alexei Kosut, Jahan Minoo
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Patent number: 8806178Abstract: A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss.Type: GrantFiled: August 14, 2013Date of Patent: August 12, 2014Assignee: International Business Machines CorporationInventors: Jane H. Bartik, Lisa C. Heller, Damian L. Osisek, Donald W. Schmidt, Patrick M. West, Jr., Phil C. Yeh
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Patent number: 8799528Abstract: One embodiment provides a data transfer device, including: a register configured to set an upper limit value for a transfer data size; and a transfer size controller configured to compare the upper limit value and the transfer data size sent from an external device, and to reduce the transfer data size when the transfer data size is larger than the upper limit value.Type: GrantFiled: February 29, 2012Date of Patent: August 5, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Takeshi Kikuchi
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Patent number: 8782628Abstract: Techniques for partitioning an operator flow graph are provided. The techniques include receiving source code for a stream processing application, wherein the source code comprises an operator flow graph, wherein the operator flow graph comprises a plurality of operators, receiving profiling data associated with the plurality of operators and one or more processing requirements of the operators, defining a candidate partition as a coalescing of one or more of the operators into one or more sets of processing elements (PEs), using the profiling data to create one or more candidate partitions of the processing elements, using the one or more candidate partitions to choose a desired partitioning of the operator flow graph, and compiling the source code into an executable code based on the desired partitioning.Type: GrantFiled: April 26, 2013Date of Patent: July 15, 2014Assignee: International Business Machines CorporationInventors: Henrique Andrade, Bugra Gedik, Kirsten W. Hildrum, Rohit M. Khandekar, Sujay S. Parekh, Deepak Rajan, Joel L. Wolf, Kun-Lung Wu
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Patent number: 8762596Abstract: A direct memory access controller is set forth. The direct memory access controller includes first and second registers storing various values that are used to set the parameters of DMA transfers that take place during a single data transaction. The first register stores a start address location value used to define a start address at which direct memory access transfers for the transaction are to begin. The second register stores a value used to end data transfers of the data transaction. The DMA controller also includes transfer control circuitry for executing the data transaction. The transfer control circuitry is adapted to automatically execute multiple, consecutive data transactions using the values stored in the first and second registers.Type: GrantFiled: February 8, 2011Date of Patent: June 24, 2014Assignee: Marvell International Ltd.Inventors: John D. Marshall, Douglas G. Keithley, William R. Schmidt
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Patent number: 8756350Abstract: An apparatus and method for tracking coherence event signals transmitted in a multiprocessor system. The apparatus comprises a coherence logic unit, each unit having a plurality of queue structures with each queue structure associated with a respective sender of event signals transmitted in the system. A timing circuit associated with a queue structure controls enqueuing and dequeuing of received coherence event signals, and, a counter tracks a number of coherence event signals remaining enqueued in the queue structure and dequeued since receipt of a timestamp signal. A counter mechanism generates an output signal indicating that all of the coherence event signals present in the queue structure at the time of receipt of the timestamp signal have been dequeued. In one embodiment, the timestamp signal is asserted at the start of a memory synchronization operation and, the output signal indicates that all coherence events present when the timestamp signal was asserted have completed.Type: GrantFiled: June 26, 2007Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Matthias A. Blumrich, Dong Chen, Alan G. Gara, Mark E. Giampapa, Philip Heidelberger, Martin Ohmacht, Valentina Salapura, Pavlos Vranas