Patents Examined by Krista Soderholm
  • Patent number: 10014276
    Abstract: A method for connecting an integrated circuit (IC) to a printed circuit board (PCB) can include the steps of fixing the IC and the PCB to a dielectric substrate. A single wire bond can be used to bond the IC to the PCB, and a ground plane can be established for the PCB. To minimize inductance losses at high frequency operation, a ground plane defect can be intentionally established by forming at least one opening in the ground plane. The opening can be rectangular when viewed in top plan, although the number of openings formed and opening geometry can be chosen according to the desired operating frequency of the device. The defect can allow for single wire bonding of the IC to the PCB in a manner which allows for high frequency operation without requiring the integration of additional matching network components on the IC and PCB.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: July 3, 2018
    Assignee: The United States of America, as Represented by the Secretary of the Navy
    Inventor: Jia-Chi Samuel Chieh
  • Patent number: 9997484
    Abstract: A semiconductor device includes a wiring substrate, a first semiconductor element, a second semiconductor element, a bump, a bonding portion, and a resin portion. The second semiconductor element is between the wiring substrate and the first semiconductor element. The bump is between the first and second semiconductor elements and electrically connects the first and second semiconductor elements. The bonding portion is between the first and second semiconductor elements, bonds the first semiconductor element to the second semiconductor element, and has a first elastic modulus. The resin portion has a second elastic modulus higher than the first elastic modulus. The resin portion is between the first and second semiconductor elements. The first semiconductor element is between a second portion of the resin portion and the wiring substrate. A third portion of the resin portion is overlapped with the first and second semiconductor elements.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: June 12, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takeori Maeda, Masatoshi Fukuda, Ryoji Matsushima, Hideo Aoki
  • Patent number: 9991178
    Abstract: An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the first surface, the second surface having a plurality of second conductive pads; a plurality of conductive through holes penetrating the first and second surfaces of the substrate and electrically connecting the first and second conductive pads; and a first removable electrical connection structure formed on the first surface and electrically connecting a portion of the first conductive pads so as to facilitate electrical testing of the interposer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: June 5, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lu-Yi Chen, Chi-Hsin Chiu, Shih-Kuang Chiu
  • Patent number: 9966449
    Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a metal contact that includes a heavy alkaline earth metal on an n-type semiconductor layer. The heavy alkaline earth metal may underlie a metal layer and/or a capping layer. Related semiconductor devices are also provided.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: May 8, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jorge A. Kittl
  • Patent number: 9966359
    Abstract: A semiconductor package may be provided. The semiconductor package may include a substrate. The semiconductor package may include a first semiconductor chip flip-chip bonded to a first surface of the substrate. The semiconductor package may include second semiconductor chips respectively flip-chip bonded to portions of the first surface of the substrate adjacent to both ends of the first semiconductor chip. The semiconductor package may include a third semiconductor chip solder-jointed to the first surface of the substrate covering the first semiconductor chip and portions of the second semiconductor chips.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: May 8, 2018
    Assignee: SK hynix Inc.
    Inventors: Sang Eun Lee, Eun Ko, Yong Jae Park
  • Patent number: 9911702
    Abstract: A semiconductor package structure and a fabrication method thereof are provided. The fabrication method comprises: providing a substrate strip, the substrate strip comprising a plurality of substrate units; disposing a plurality of chips on the plurality of substrate units; disposing a packaging encapsulant on the substrate strip to encapsulate the chips; forming a warp-resistant layer on a top surface of the packaging encapsulant; and dividing the substrate strip to separate the plurality of substrate units to further fabricate a plurality of semiconductor package structures, wherein the warp-resistant layer is formed of a selected material with a selected thickness to make a variation of warpage of the semiconductor package structure at a temperature between 25° C. and 260° C. to be smaller than 560 ?m.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: March 6, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tien-Szu Chen, Sheng-Ming Wang, Kuang-Hsiung Chen, Yu-Ying Lee
  • Patent number: 9905491
    Abstract: Semiconductor packages with multiple substrates can incorporate cavities in a portion of an upper substrate to minimize or reduce void formations during a molding process. The cavities can be formed substantially over the integrated circuit devices and not over the internal interconnects to further facilitate the flow of the molding compound. The combination with extension members or recesses on a top or exterior surface of the upper substrate can further cut down on bleeding or spill over of the molding compound between adjacent packages and improve device reliability and yield.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: February 27, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: In Sang Yoon, DeokKyung Yang, SeongHun Mun
  • Patent number: 9892957
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first dielectric layer over the substrate. The semiconductor device structure includes a second dielectric layer over the first dielectric layer. The first dielectric layer and the second dielectric layer are made of different materials. The semiconductor device structure includes a conductive via structure passing through the first dielectric layer and penetrating into the second dielectric layer. The conductive via structure has a first portion and a second portion. The first portion and the second portion are in the first dielectric layer and the second dielectric layer respectively. The first portion has a first end portion facing the substrate. A first width of the first end portion is greater than a second width of the second portion.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: February 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Ting Chen, Che-Cheng Chang, Chen-Hsiang Lu, Yu-Cheng Liu
  • Patent number: 9887166
    Abstract: An assembly with modules (110, 1310) containing integrated circuits and attached to a wiring substrate (120) is reinforced by one or more reinforcement frames (410) attached to the wiring substrate. The modules are located in openings (e.g. cavities and/or through-holes 414) in the reinforcement frame. Other features are also provided.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: February 6, 2018
    Assignee: Invensas Corporation
    Inventors: Rajesh Katkar, Laura Wills Mirkarimi, Arkalgud R. Sitaram, Charles G. Woychik
  • Patent number: 9859199
    Abstract: A method of forming a semiconductor package includes growing a layer of carbon nano material on a chip. The chip has a first surface and a second surface and the layer of carbon nano material is grown on the first surface of the chip. The layer of carbon nano material is configured to provide a path through which heat generated from the chip is dissipated. A substrate is attached to the second surface of the chip. A molding compound is formed above the substrate to encapsulate the chip and the layer of carbon nano material.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hao Tseng, Ying-Hao Kuo, Kuo-Chung Yee
  • Patent number: 9842765
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a dielectric layer over the substrate. The dielectric layer has a trench. The semiconductor device structure includes a conductive line in the trench. The conductive line has a first end portion and a second end portion. The first end portion faces the substrate. The second end portion faces away from the substrate. A first width of the first end portion is greater than a second width of the second end portion.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: December 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Ting Chen, Che-Cheng Chang, Chen-Hsiang Lu, Yu-Cheng Liu
  • Patent number: 9837347
    Abstract: A coaxial copper pillar for signal transmission with signal shield is disclosed so that signal integrity for the signal passes transmission is maintained. One embodiment shows at least one coaxial copper pillar is made as a terminal connector for a chip package, the coaxial copper pillars are made adaptive for electrically coupling the chip package to a mother board.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: December 5, 2017
    Inventor: Dyi-Chung Hu
  • Patent number: 9812409
    Abstract: A method includes providing a substrate having a seal ring region and a circuit region, forming a seal ring structure over the seal ring region, forming a first frontside passivation layer above the seal ring structure, etching a frontside aperture in the first frontside passivation layer adjacent to an exterior portion of the seal ring structure, forming a frontside metal pad in the frontside aperture to couple the frontside metal pad to the exterior portion of the seal ring structure, forming a first backside passivation layer below the seal ring structure, etching a backside aperture in the first backside passivation layer adjacent to the exterior portion of the seal ring structure, and forming a backside metal pad in the backside aperture to couple the backside metal pad to the exterior portion of the seal ring structure. Semiconductor devices fabricated by such a method are also provided.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: November 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Hsin-Hui Lee, Wen-De Wang, Shu-Ting Tsai
  • Patent number: 9793212
    Abstract: An embodiment semiconductor device includes a first conductive feature in a dielectric layer and a second conductive feature over the dielectric layer and electrically connected to the first conductive feature. The second conductive feature includes a dual damascene structure and further includes a top portion within both a line portion and a via portion of the second conductive feature and a bottom portion in the via portion of the second conductive feature. The bottom portion comprises a different conductive material than the top portion, and a thickness of the bottom portion is at least about twenty percent of a total thickness of the via portion of the second conductive feature.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: October 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chun Huang, Chih-Hsiang Yao, Jye-Yen Cheng, Wen-Chuan Chiang, Ying-Wen Huang
  • Patent number: 9780063
    Abstract: A semiconductor wafer has a plurality of semiconductor die with contact pads for electrical interconnect. An insulating layer is formed over the semiconductor wafer. A bump structure is formed over the contact pads. The bump structure has a buffer layer formed over the insulating layer and contact pad. A portion of the buffer layer is removed to expose the contact pad and an outer portion of the insulating layer. A UBM layer is formed over the buffer layer and contact pad. The UBM layer follows a contour of the buffer layer and contact pad. A ring-shaped conductive pillar is formed over the UBM layer using a patterned photoresist layer filled with electrically conductive material. A conductive barrier layer is formed over the ring-shaped conductive pillar. A bump is formed over the conductive barrier layer. The buffer layer reduces thermal and mechanical stress on the bump and contact pad.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: October 3, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: JoonYoung Choi, YoungJoon Kim, SungWon Cho
  • Patent number: 9780031
    Abstract: Wiring structures with dummy metal features and methods of manufacture are disclosed. A structure includes a metal wiring structure, and dummy metal features in electrical and direct physical contact with the metal wiring structure in a same plane as the metal wiring structure. The dummy metal features do not change a resistance of the metal wiring structure and are remote from other structures.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: October 3, 2017
    Assignee: GLOBALFOUDRIES INC.
    Inventors: Fen Chen, Cathryn J. Christiansen, Roger A. Dufresne, Charles W. Griffin
  • Patent number: 9761561
    Abstract: Semiconductor devices and methods of forming a semiconductor device are disclosed. The device includes a wafer with top and bottom surfaces. The wafer includes edge and non-edge regions. The wafer includes a plurality of devices and partially processed TSV contacts disposed in the non-edge region and a groove disposed at the edge region. The groove enables edges of the wafer to be automatically trimmed off as the wafer is subject to a back-grinding planarization process to expose the TSV contacts in the non-edge region of the wafer.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: September 12, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Ranjan Rajoo, Kai Chong Chan
  • Patent number: 9741696
    Abstract: An apparatus relates generally to a three-dimensional stacked integrated circuit. In such an apparatus, the three-dimensional stacked integrated circuit has at least a first die and a second die interconnected to one another using die-to-die interconnects. A substrate of the first die has at least one thermal via structure extending from a lower surface of the substrate toward a well of the substrate without extending to the well and without extending through the substrate. A first end of the at least one thermal via structure is at least sufficiently proximate to the well of the substrate for conduction of heat away therefrom. The substrate has at least one through substrate via structure extending from the lower surface of the substrate to an upper surface of the substrate. A second end of the at least one thermal via structure is coupled to at least one through die via structure of the second die for thermal conductivity.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: August 22, 2017
    Assignee: Invensas Corporation
    Inventors: Rajesh Katkar, Arkalgud R. Sitaram, Cyprian Emeka Uzoh
  • Patent number: 9741644
    Abstract: A stacked integrated circuit (IC) system including a substrate, a contour support, and a first and second IC dies. The contour support including a first support frame attached to the substrate defining a first lateral contact surface substantially orthogonal to the substrate, a support plate on the first support frame substantially parallel to the substrate, and a second support frame on the support plate defining a second lateral contact surface substantially orthogonal to the substrate, with the first and second lateral contact surfaces laterally offset from each other. The first integrated circuit die with a side abutting the first lateral contact surface, the second integrated circuit die with a side abutting the second lateral contact surface such that at least a portion of the support plate is between the first and second integrated circuit dies.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: August 22, 2017
    Assignee: Honeywell International Inc.
    Inventors: Romney R. Katti, James L. Tucker
  • Patent number: 9735082
    Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Chi-Hsi Wu, Shin-Puu Jeng