Patents Examined by Krista Soderholm
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Patent number: 9406575Abstract: A pixel array substrate including a substrate and pixel units arranged in an array on the substrate is provided. Each pixel unit includes a TFT having a source, a gate, and a drain, a pixel electrode electrically connected to the drain, a common electrode, an insulation layer, and a test electrode. The pixel electrode is located between the common electrode and the substrate. The common electrode has slits that expose the pixel electrode. The insulation layer is located between the common electrode and the pixel electrode and has a contact hole exposing the pixel electrode. The test electrode and the common electrode belong to the same film layer, and the test electrode is separated from the common electrode. The contact hole is filled with the test electrode, and the test electrode is electrically connected to the drain. A display panel including the pixel array substrate is also provided.Type: GrantFiled: January 27, 2014Date of Patent: August 2, 2016Assignee: Chunghwa Picture Tubes, LTD.Inventors: Tzu-Chiang Liao, Chih-Wen Lai
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Patent number: 9379045Abstract: A first embodiment is a common drain+clip 20. It has a conventional drain contact on its bottom surface and is flip chip mounted on a half-etched leadframe 40 which has external source, gate and drain contacts connected to the sources, gate and common drain of the die 20. Common drain clip 50 connects the drain 30 to external contacts between opposite gate contacts. A second embodiment is a direct drain embodiment+heatslug. The device 80 has a top drain contact 36 that extends to the common drain 30 across the bottom of the die which is flip chip mounted to a half-etched leadframe having external source, gate and drain contacts connected to the sources, gates and common drain of the die 80.Type: GrantFiled: September 13, 2013Date of Patent: June 28, 2016Assignee: Fairchild Semiconductor CorporationInventors: Chung-Lin Wu, Steven Sapp, Bigildis Dosdos, Suresh Belani, Sunggeun Yoon
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Patent number: 9368479Abstract: An apparatus relates generally to a three-dimensional stacked integrated circuit. In such an apparatus, the three-dimensional stacked integrated circuit has at least a first die and a second die interconnected to one another using die-to-die interconnects. A substrate of the first die has at least one thermal via structure extending from a lower surface of the substrate toward a well of the substrate without extending to the well and without extending through the substrate. A first end of the at least one thermal via structure is at least sufficiently proximate to the well of the substrate for conduction of heat away therefrom. The substrate has at least one through substrate via structure extending from the lower surface of the substrate to an upper surface of the substrate. A second end of the at least one thermal via structure is coupled to at least one through die via structure of the second die for thermal conductivity.Type: GrantFiled: March 7, 2014Date of Patent: June 14, 2016Assignee: Invensas CorporationInventors: Rajesh Katkar, Arkalgud R. Sitaram, Cyprian Emeka Uzoh
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Patent number: 9368434Abstract: In an embodiment, an electronic component includes a housing, a die pad having a first surface and a second surface opposing the first surface, a first high voltage semiconductor device arranged on the first surface of the die pad, a further semiconductor device arranged on the second surface of the die pad and a conductive connection between the first high voltage semiconductor device and the further semiconductor device. The conductive connection is surrounded by the housing and includes a portion arranged adjacent the die pad.Type: GrantFiled: November 27, 2013Date of Patent: June 14, 2016Assignee: Infineon Technologies AGInventor: Ralf Otremba
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Patent number: 9355997Abstract: An assembly with modules (110, 1310) containing integrated circuits and attached to a wiring substrate (120) is reinforced by one or more reinforcement frames (410) attached to the wiring substrate. The modules are located in openings (e.g. cavities and/or through-holes 414) in the reinforcement frame. Other features are also provided.Type: GrantFiled: May 27, 2014Date of Patent: May 31, 2016Assignee: Invensas CorporationInventors: Rajesh Katkar, Laura Wills Mirkarimi, Arkalgud Sitaram, Charles G. Woychik
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Patent number: 9343382Abstract: An electronic device includes a substrate; an element configured to be formed on the substrate; a sidewall member configured to enclose the element on the substrate; a cover member configured to be disposed on the sidewall member, and to partition a space around the element along with the sidewall member on the substrate; and a seal member configured to be disposed outside of the sidewall member, to bond the sidewall member and the cover member to a surface of the substrate, and to seal the space.Type: GrantFiled: April 11, 2014Date of Patent: May 17, 2016Assignee: FUJITSU LIMITEDInventor: Takeaki Shimanouchi
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Patent number: 9308571Abstract: An apparatus comprising a first substrate having a first surface, a second substrate having a second surface facing the first surface and an array of metallic raised features being in contact with the first surface to the second surface, a portion of the raised features having a mechanical bend or buckle plastic deformation produced therein via a compressive force. One or more of the metallic raised features has one or more surface singularities therein prior to the mechanical bend or the buckle plastic deformation produced by the compressive force.Type: GrantFiled: September 19, 2014Date of Patent: April 12, 2016Assignee: Alcatel LucentInventors: Roger Scott Kempers, Shankar Krishnan, Alan Michael Lyons, Todd Richard Salamon
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Patent number: 9305912Abstract: A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.Type: GrantFiled: June 9, 2015Date of Patent: April 5, 2016Assignee: SK Hynix Inc.Inventors: Hee Min Shin, Cheol Ho Joh, Eun Hye Do, Ji Eun Kim, Kyu Won Lee
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Patent number: 9287239Abstract: An integrated circuit die includes conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof. The integrated circuit also includes a core circuit located outside the contiguous region. The core circuit is coupled to at least one of the connection sites.Type: GrantFiled: April 13, 2011Date of Patent: March 15, 2016Assignee: Rambus Inc.Inventors: Frederick A. Ware, Ely Tsern, Thomas Vogelsang
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Patent number: 9287238Abstract: A semiconductor package includes a plurality of bond pads having a first side and a second side opposing the first side, a coating covering the first side of the bond pads, semiconductor dies and electrical conductors attached to the second side of the bond pads, and a molding compound encasing the semiconductor dies and the electrical conductors at the second side of the bonds pads. The molding compound has a first side through which the bond pads protrude and a second side opposing the first side, the first side of the molding compound having a planar surface between adjacent ones of the bond pads. The package further includes a material plated on exposed sidewalls of the bonds pads uncovered by the molding compound and which is detectable by optical inspection. A corresponding method of manufacture is also provided.Type: GrantFiled: December 2, 2013Date of Patent: March 15, 2016Assignee: Infineon Technologies AGInventors: Soon Lock Goh, Swee Kah Lee
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Patent number: 9252070Abstract: A three-dimensional mounting semiconductor device includes a layer structure including a plurality of first substrates with a trench-shaped concavity formed in and a plurality of second substrates with semiconductor elements formed in, which are alternately stacked, wherein an unevenness defined by a size difference between the first substrate and the second substrate is formed on a side surface, and a first through-hole are defined by an inside surface of the trench-shaped concavity and a surface of the second substrate, and a third substrate jointed to the side surface of the layer structure and having an unevenness formed on a surface jointed to the layer structure which are engaged with the unevenness formed on the side surface of the layer structure.Type: GrantFiled: September 30, 2013Date of Patent: February 2, 2016Assignee: FUJITSU LIMITEDInventors: Yoshihiro Mizuno, Norinao Kouma, Osamu Tsuboi
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Patent number: 9240391Abstract: A semiconductor device includes: a first semiconductor chip; a second semiconductor chip placed such that a front face of the second semiconductor chip faces a front face of the first semiconductor chip, and being smaller in size than the first semiconductor chip; an expansion portion extending outward from at least one side face of the second semiconductor chip; a wiring board placed such that a front face of the wiring board faces the front face of the first semiconductor chip and a back face of the second semiconductor chip; and a first interconnect formed on the back face of the second semiconductor chip and a back face of the expansion portion, and being in connection to the wiring board.Type: GrantFiled: December 26, 2013Date of Patent: January 19, 2016Assignee: Panasonic CorporationInventors: Noriyuki Nagai, Shigefumi Dohi
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Patent number: 9236360Abstract: An IC chip package and a chip-on-glass structure using the same are provided. The IC chip package includes an IC chip having a circuit surface, and plural copper (Cu) bumps formed on the circuit surface. Moreover, a non-conductive film (NCF) could be formed on the circuit surface to cover the Cu bumps. The chip-on-glass structure includes a glass substrate, plural electrodes such as aluminum (Al) electrodes formed on the glass substrate, and a conductive film formed on the electrodes. The conductive film contains a number of conductive particles. When the IC chip package is coupled to the glass substrate, the Cu bumps can be coupled to the corresponding electrodes via conductive particles.Type: GrantFiled: October 12, 2012Date of Patent: January 12, 2016Assignee: NOVATEK MICROELECTRONICS CORP.Inventor: Tai-Hung Lin
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Patent number: 9219025Abstract: A molded flip-chip semiconductor package includes a leadframe having opposing first and second main surfaces, a first metallization on the first main surface, a second metallization on the second main surface, recessed regions which extend from the second main surface toward the first main surface, and spaced apart leads chemically etched into the leadframe between gaps in the first metallization. The package further includes a semiconductor die having a plurality of pads facing and attached to the leads of the leadframe, a first molding compound that fills the recessed regions, and a second molding compound that encases the semiconductor die and fills the space between the leads such that the second molding compound abuts the first molding compound. A is the overall thickness of the leadframe, B is the spacing between adjacent ones of the leads, and B/A<1.Type: GrantFiled: August 15, 2014Date of Patent: December 22, 2015Assignee: Infineon Technologies AGInventors: Swee Kah Lee, Chee Hong Fang, Mei Chin Ng
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Patent number: 9209105Abstract: Provided herein are electronic devices assembled with thermally insulating layers.Type: GrantFiled: May 1, 2014Date of Patent: December 8, 2015Assignee: Henkel IP & Holding GmbHInventors: My Nhu Nguyen, Emilie Barriau, Martin Renkel, Matthew J. Holloway, Jason Brandi
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Patent number: 9209104Abstract: Provided herein are electronic devices assembled with thermally insulating layers.Type: GrantFiled: May 1, 2014Date of Patent: December 8, 2015Assignee: Henkel IP & Holding GmbHInventors: My Nhu Nguyen, Jason Brandi
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Patent number: 9172143Abstract: An electronic device module as described herein includes an electronic device package having device contacts. The electronic device package is fixed within encapsulating material, along with an electrically conductive ground layer. The ground layer has a device opening in which the electronic device package resides, and the ground layer also has an antenna opening spaced apart from the device opening. The device contacts and one side of the ground layer correspond to a first surface, and a patch antenna element overlies the first surface. The antenna element is coupled to the electronic device package, and a projection of the patch antenna element onto the first surface resides within the antenna opening. Also provided are methods for manufacturing such an electronic device module.Type: GrantFiled: January 28, 2013Date of Patent: October 27, 2015Assignee: FREESCALE SEMICONDUCTOR INC.Inventor: Jinbang Tang
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Patent number: 9159687Abstract: A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1.Type: GrantFiled: August 10, 2012Date of Patent: October 13, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Hua Chang, Cheng-Lin Huang, Jing-Cheng Lin
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Patent number: 9136277Abstract: A three dimensional stacked semiconductor structure comprises a stack including plural oxide layers and conductive layers arranged alternately, at least a contact hole formed vertically to the oxide layers and the conductive layers, and extending to one of the conductive layers, an insulator formed at the sidewall of the contact hole, a conductor formed in the contact hole and connecting the corresponding conductive layer, and the corresponding conductive layer comprises a silicide. The silicide could be formed at edges or an entire body of the corresponding conductive layer. Besides the silicide, the corresponding conductive layer could, partially or completely, further comprise a conductive material connected to the conductor. The corresponding conductive layer which the contact hole extends to has higher conductivity than other conductive layers. Also, the 3D stacked semiconductor structure could be applied to a fan-out region of a 3D flash memory.Type: GrantFiled: October 16, 2012Date of Patent: September 15, 2015Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Erh-Kun Lai, Yen-Hao Shih
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Patent number: 9105463Abstract: A semiconductor device includes an extended semiconductor chip including a first semiconductor chip and an extension outwardly extending from a side surface of the first semiconductor chip; and a second semiconductor chip connected to the extended semiconductor chip through a plurality of bumps and electrically connected to the first semiconductor chip. The first semiconductor chip is smaller than the second semiconductor chip. At least one external terminal is provided on the extension.Type: GrantFiled: December 26, 2013Date of Patent: August 11, 2015Assignee: Panasonic CorporationInventors: Kenji Yokoyama, Takeshi Kawabata, Kiyomi Hagihara