Abstract: According to various embodiments, a logic gate device includes a transistor, a first resistor, a second resistor and a third resistor. The first resistor is connected between a first input terminal of the logic gate device and a gate terminal of the transistor. The second resistor is connected between a second input terminal of the logic gate device and the gate terminal. The third resistor is connected between a voltage supply terminal and a first terminal of the transistor. The logic gate device is configured to generate an output voltage at the first terminal based on input voltages received at the first input terminal and the second input terminal.

Abstract: An integrated circuit includes: a flip-flop circuit arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode; and a gating circuit coupled to the flip-flop circuit, for generating the first clock signal and the second clock signal according to the master signal and an input clock signal; wherein a first signal transition number of the first clock signal and a second signal transition number of the second clock signal are not greater than a third signal transition number of the input clock signal during the writing mode and the storing mode.

Abstract: Methods, systems and apparatus for producing quantum circuits with low T gate counts. In one aspect, a method for performing a temporary logical AND operation on two control qubits includes the actions of obtaining an ancilla qubit in an A-state; computing a logical-AND of the two control qubits and storing the computed logical-AND in the state of the ancilla qubit, comprising replacing the A-state of the ancilla qubit with the logical-AND of the two control qubits; maintaining the ancilla qubit storing the logical-AND of the two controls until a first condition is satisfied; and erasing the ancilla qubit when the first condition is satisfied.

Abstract: A plasma processing method is performed by a plasma processing apparatus that includes a process chamber, a conductive first component that is disposed in the process chamber and at least a surface of which is covered with a conductive silicon material, and a second component that is disposed in the process chamber and is at a ground potential or a floating potential with respect to an electric potential of plasma. The method includes forming an oxide layer on the surface of the first component by converting an oxygen-containing gas into plasm, and treating a surface of the second component by converting a halogen-containing gas into plasm.

Abstract: A device includes a microwave generation unit that averages the first measured values and the second measured values at a predetermined movement average time and a predetermined sampling interval, and controls the microwave such that a value obtained by subtracting the averaged second measured value from the averaged first measured value comes close to the setting power, and in which the predetermined movement average time is 60 ?s or less, and a relationship of y?78.178x0.1775 is satisfied when the predetermined sampling interval is indicated by x, and the predetermined movement average time is indicated by y.

Abstract: The present invention relates to a self-destructible apparatus and method. The apparatus includes a self-destructible operation unit composed of a plurality of cavity cells; a variable voltage/current supply unit configured to supply a variable voltage and current to the self-destructible operation unit; an identification (ID) matching unit configured to compare an ID input from an external source to a digital physical unclonable function (PUF) ID assigned to each of the cavity cells to determine whether the two IDs match each other so that power of the variable voltage/current supply unit is supplied to only a desired cavity cell among the plurality of cavity cells; a digital PUF ID generation unit configured to generate the digital PUF ID input to the ID matching unit; and an external ID input unit configured to generate the ID input to the ID matching unit.

Abstract: Described is a high speed, low power level shifter circuit which includes a level shifter coupled to a sensing circuit. The level shifter includes a pair of source transistors, a pair of input transistors, and a pair of switching circuits connected between the source transistors and the input transistors. The sensing circuit turns off a switching circuit on an active side of the level shifter based on detecting that an output voltage of the level shifter has completed a voltage level transition from a first logic level voltage to a second logic level voltage. An open circuit is established on the active side and turns off the pair of source transistors. The other switching circuit is turned on. Static current flow on the active side of the level shifter is stopped and the output voltage is latched to a voltage representative of the second logic level voltage.

Abstract: A driver is provided for driving at least two sets of solid state lighting elements. A switched capacitor power converter is provided, and a switch arrangement is used for selectively connecting a first set and a second set of solid state lighting elements in series connection at the output of the power converter or connecting the first set of solid state lighting elements at the output of the power converter without the second set of solid state lighting elements. A first duty cycle of the switched capacitor power converter and a second duty cycle control of the switch arrangement are both controlled. In this driver design, a switched capacitor power converter and a switch arrangement are independently controlled using a duty cycle approach. The switched capacitor power converter is used to provide current control, and the switch arrangement is used to control whether the second set of lighting elements is connected to the output or not.

Abstract: A reconfigurable circuit includes: a first line; a first switch element disposed between the first line and a first power source line of first voltage; a second line; a second switch element disposed between the second line and a second power source line of second voltage which is different from the first voltage; and a resistive switch assembly disposed between the first line and the second line. The resistive switch assembly includes: a first non-volatile resistive switch; and a second non-volatile resistive switch whose first end is coupled to a first end of the first non-volatile resistive switch. The second end of the first non-volatile resistive switch is coupled to the first line, and the second end of the second non-volatile resistive switch is coupled to the second line.

Abstract: Devices, circuits, and methods for fabricating circuits. A device having ambipolar characteristics includes a semiconductor layer and multiple gates, a source contact, and a drain contact coupled to the semiconductor layer. One channel may have elections as the majority charge carrier and may be formed proximate to one of the gates. Another channel may have holes as the majority charge carrier and be formed proximate another gate. Each of the channels is generally parallel to the other and couples the source contact to the drain contact. The device may be optimized by adjusting the work-functions in one or more of source and drain contacts or gates to compensate for differences in the effective masses of the majority carriers in each of the channels. The ambipolar nature of the devices allows logic circuits to be fabricated using one or two of the devices.

Abstract: An emission driver includes a latch circuit and a buffer circuit. The latch circuit receives a first signal, a second signal, and a first clock signal. The latch circuit includes a first output terminal and a second output terminal. The first output terminal of the latch circuit outputs a third signal according to the first clock signal. The second output terminal of the latch circuit outputs a fourth signal in reverse to the third signal according to the first clock signal. The buffer circuit includes a first input terminal, a second input terminal and a third output terminal. The first input terminal of the buffer circuit receives the third signal. The second input terminal of the buffer circuit receives the fourth signal. The third output terminal of the buffer circuit outputs an emission signal according to the third signal and the fourth signal.

Abstract: The present technology relates to a driver circuit, a control method therefor, and a transmission/reception system that enable implementation of a large amplitude signal output required for long distance transmission with low power consumption. The driver circuit includes: a current drive circuit that outputs a predetermined current; and a termination resistance circuit connected in parallel with the current drive circuit, in which the termination resistance circuit connects a termination resistance to a transmission line when the current drive circuit outputs a current, and disconnects the termination resistance from the transmission line when the current drive circuit does not output the current. The present technology can be applied to, for example, a driver circuit that outputs a signal to a long distance transmission line, and the like.

Abstract: Methods, systems, and devices for drive strength calibration for multi-level signaling are described. A driver may be configured to have an initial drive strength and to drive an output pin of a transmitting device toward an intermediate voltage level of a multi-level modulation scheme, where the output pin is coupled with a receiving device via a channel. The receiving device may generate, and the transmitting device may receive, a feedback signal indicating a relationship between the resulting voltage of the channel and an value for the intermediate voltage level. The transmitting device may determine and configure the driver to use an adjusted drive strength for the intermediate voltage level based on the feedback signal. The driver may be calibrated (e.g., independently) for each intermediate voltage level of the multi-level modulation scheme. Further, the driver may be calibrated for the associated channel.

Abstract: An impedance matching device includes: a variable capacitor in which a plurality of series circuits of capacitors and semiconductor switches are connected in parallel; a calculation unit that calculates an impedance or a reflection coefficient on the load side using information regarding impedance acquired from the outside; and a control unit that determines ON/OFF states to be taken by the semiconductor switches included in the variable capacitor using the impedance or the reflection coefficient calculated by the calculation unit and turns on or off the semiconductor switches based on the determined states. The control unit changes an ON/OFF control timing between one and another of the semiconductor switches.

Abstract: Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns; clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

Abstract: There is described a microwave device and methods of operating same. The device comprises at least one superconducting qubit coupled to a transmission line defining a first port, and a filter. The filter comprises a first resonant element having a first resonance frequency f1, positioned along the transmission line between the first port and the qubit, and a second resonant element having a second resonance frequency f2 different from f1 and positioned along the transmission line between the first resonant element and the qubit.

Abstract: An embodiment includes (CR) gate having a first control qubit coupled with a first target qubit, and a second CR gate having a second control qubit coupled with a second target qubit and the first control qubit. The embodiment also includes controller circuitry for performing operations including first and second iterations of: during a first time period, directing respective CR pulses to the first and second control qubits; during a second time period, directing respective single qubit pulses to the first control qubit and to the second target qubit; during a third time period, directing respective CR pulses to the first and second control qubits; and during a fourth time period, directing respective single qubit pulses to the second control qubit and to the first target qubit.

Abstract: An adder uses with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are the same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals to the majority gates can be analog, digital, or a combination of them, which are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate.

Abstract: The various embodiments described herein include methods, devices, and systems for operating superconducting circuitry. In one aspect, a programmable circuit includes: (1) a superconducting component arranged in a multi-dimensional array of alternating narrow and wide portions, the superconducting component having an input terminal at a first end and an output terminal at a second end opposite of the first end; and (2) control circuitry coupled to the narrow portions of the superconducting component, the control circuitry configured to transition the narrow portions between superconducting and non-superconducting states.

Abstract: Methods, systems, and computer programs are presented for distributing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an iNOC comprising iNOC rows and iNOC columns; a set of clusters coupled to the iNOC, each cluster comprising a vertical network access point (NAP) for iNOC column communications, a horizontal NAP for iNOC row communications, a valid signal, and programmable logic, where the vertical NAP is connected to the horizontal NAP when the valid signal is activated; and an Ethernet controller coupled to the iNOC, the Ethernet controller configurable to send Ethernet-packet segments to the vertical NAPs.