Abstract: A wireless lighting control system is provided to create a lighting pattern by remotely controlling a plurality of lighting devices according to groups, thereby improving a lighting effect. The wireless lighting control system includes a first lighting device electrically connected with a first smart device to act as a master, and a plurality of second lighting devices electrically connected with a plurality of second smart devices to act as slaves, respectively. If a group for lighting control and control pattern information according to groups are selected from the first smart device, the first lighting device transmits the control pattern information according to the groups to the second lighting devices through a wireless communication scheme. At least one of lighting units of the second lighting devices and display units of the second smart devices is controlled based on the control pattern information according to the groups.

Abstract: Exterior lighting systems are provided for towed vehicles, such as towed RVs, which includes a control module for receiving conventional illumination signals from the towing vehicle through a conventional trailer plug, and supplementing those conventional illumination signals with synchronized supplemental LED lighting. That supplemental lighting can include “constant-on” flashing LEDs indicative of operator intentions in the towing vehicle, either at locations adjacent conventional exterior lighting or other locations on the trailer. The control module can also support supplemental exterior illumination of the RV when the towed vehicle is stationary and in use for camping or advertisement. The control module includes a failsafe mode in the event of a fault in the supplemental lighting (so as to maintain conventional exterior lighting capability), diagnostic LED output for troubleshooting, and an automatic reset feature.

Abstract: Ring packet built-in self-test (PBIST) circuitry configured to detect errors in wires connecting a ring of superconducting chips includes circuitry configured to make the PBIST immune to interchip latency and still allow the PBIST to test a stop-to-stop connection. By making a PBIST independent of latency, an entire ring can be characterized for latency and for its bit-error rate prior to running any functional test. Such systems and associated methods can be scaled to larger platforms having any number of ring stops. The PBIST circuitry can function as either transmitter or receiver, or both, to test an entire ring. The PBIST can also be used to tune clocks in the ring to achieve the lowest overall bit error rate (BER) in the ring.

Abstract: The invention relates to a luminaire comprising a housing comprising an electrically nonconductive portion; a light source arranged in the housing; a light drive and control assembly and configured for driving said light source; a communication assembly arranged in the housing.

Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.

Abstract: A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.

Abstract: A method and apparatus for a light fixture that uses current sharing across any one or more parallel LED strings within the light fixture. A processor determines the current requirements of the one or more LED strings that are needed to produce a given intensity level. The processor then apportions the current generation capability of a power supply across all active LED strings using time division multiple access (TDMA) whereby each LED string conducts its apportioned current within its allocated time slot to the mutual exclusion of the remaining active LED strings in any given time period. The light fixture utilizes LEDs with increased forward voltage interspersed with LEDs having reduced forward voltage in the same LED string. A processor utilizes shunt devices across the one or more LEDs with increased forward voltage to substantially match the cumulative forward voltage of each LED string.

Abstract: A method includes executing a calibration operation on a set of qubits, in a first iteration, to produce a set of parameters, a first subset of the set of parameters corresponding to a first qubit of the set of qubits, and a second subset of the set of parameters corresponding to a second qubit of the set of qubits. In an embodiment, the method includes selecting the first qubit, responsive to a parameter of the first subset meeting an acceptability criterion. In an embodiment, the method includes forming a quantum gate, responsive to a second parameter of the second subset failing to meet a second acceptability criterion, using the first qubit and a third qubit.

Abstract: Provided is a logic circuit comprising: a switch portion that includes one or more switching devices configured to be turned on and off in accordance with an input signal and is configured to generate an output signal with a logical value according to an operating state of the switching devices; and a clamp portion configured to clamp a voltage of the output signal, of a case where the logical value of the output signal is logic H. The switch portion may be arranged between an output line and a reference potential line, and the clamp portion may be arranged in parallel with the switch portion, between the output line and the reference potential line. The logic circuit may include a current suppression portion configured to suppress a current flowing through the clamp portion, when the logical value of the output signal is logic H.

Abstract: A cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, a battery-indifferent or pure energy harvesting multi-mode system, a method of operating a cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, and a method of operating battery-indifferent or pure energy harvesting multi-mode system.

Abstract: An impedance calibration circuit may include: a first driver having an impedance calibrated according to a first impedance control code, and configured to drive an output terminal according to first data; a second driver having an impedance calibrated according to a second impedance control code, and configured to drive the output terminal according to second data; and an impedance calibration circuit configured to calibrate the first impedance control code to a first target value set to a resistance value of an external resistor, and calibrate the second impedance control code to a second target value different from the resistance value of the external resistor.

Abstract: Logic circuitry includes a first logic circuit, second logic circuits, a third logic circuit, and fourth logic circuits. The first logic circuit inverts a first output signal relative to an input signal only in response to a first control signal having a first state that indicates that the input signal has remained in a same logic state for at least a predefined period of time. The second logic circuits are coupled in series. The second logic circuits generate a second output signal in response to the first output signal. The third logic circuit inverts a third output signal relative to the second output signal only in response to the first control signal having the first state. The fourth logic circuits are coupled in series. The fourth logic circuits generate a fourth output signal in response to the third output signal.

Abstract: According to one embodiment, an integrated electronic circuit has a switching network configured to receive binary control states, one or more secret-carrying gates, wherein each secret-carrying gate represents Boolean secrets and is configured to receive binary input states and to output one or more Boolean secrets according to a state sequence of the binary input states, and one or more flip-flops configured to store binary output states output by the switching network and to supply binary input states to the one or more secret-carrying gates based on the stored binary output states. The switching network generates the binary output states by combining the binary control states and Boolean secrets output by the one or more secret-carrying gates. The integrated electronic circuit outputs Boolean secrets from the one or more secret-carrying gates and/or the binary output states from the switching network to another integrated electronic circuit.

Abstract: A reversible logic circuit and an operation method thereof are provided. The logic circuit includes resistive switching cells, word lines, and bit lines. The word lines and the bit lines are perpendicular to each other. The anode of a resistive switching cell is connected to the word line as a first input terminal to apply logic operating voltage or be grounded. The cathode of a resistive switching cell is connected to the bit line as a second input terminal to apply logic operating voltage or be grounded. When performing reversible logic operation, four levels of resistance states of the resistive switching cell are used as logic outputs to implement single-input NOT and dual-input C-NOT reversible logic functions.

Abstract: The invention relates to an electronic database (101) having entries for a plurality of operating devices (151) and a plurality of lamps (152), which electronic database is searched on the basis of a query (115). The query (115) indicates a light characteristic. On the basis of the search of the electronic database (101), a combination of a selected operating device and a selected lamp is determined and an electrical operating point of the selected operating device is determined. Then, an output (116) is provided, which indicates the selected operating device, the selected lamp and the determined operating point.

Abstract: Systems for monitoring or control can include reconfigurable input and output channels. Such reconfigurable channels can include as few as a single terminal and a ground pin, or such channels can include three or four terminal configuration such as for use in four-terminal resistance measurements. Channel reconfiguration can be accomplished such as using software-enabled or firmware-enabled control of channel hardware. Such channel hardware can include analog-to-digital and digital-to-analog conversion capability, including use of a digital-to-analog converter to provide field power or biasing. In an example, compensation can be provided to suppress a leakage current from flowing through a digital output to a load connected to the reconfigurable channel terminal, particularly when the digital output is disabled.

Abstract: The present disclosure provides circuits and methods that can be used to update configurations. An example circuit can include a plurality hLUTs and a plurality of registers configured to propagate a set of data or a portion thereof to the plurality of hLUTs. An hLUT of the plurality of hLUTs can have a transformation unit comprising transformation circuitry configured to (i) receive the set of data or the portion thereof from a register of the plurality of registers and (ii) transform the set of data or the portion thereof into configurations for the hLUT.

Abstract: An integrated circuit includes first circuits that are configured to implement a user design for the integrated circuit, second circuits that are unused by the user design, and configuration circuitry that couples the second circuits together through a network of conductors. Transistors in the second circuits turn on and off in response to a varying signal that propagates through the second circuits and through the network of conductors while the first circuits implement the user design.

Abstract: A waveguide has a first conductor surface facing toward the interior of the waveguide, a second conductor surface facing toward the interior of the waveguide, and a slot extending from the first conductor surface to the outside of the waveguide. The first conductor surface and the second conductor surface electrically communicate with each other and face each other. The first length in the y direction of the first conductor surface in a cross section perpendicular to the z direction is smaller than the second length in the y direction of the second conductor surface in the cross section perpendicular to the z direction. The first length includes the length in the y direction of the slot in the cross section perpendicular to the z direction. The second length is smaller than the distance between the first conductor surface and the second conductor surface in the x direction.

Abstract: A CMOS transistor circuit including: a first block generating a first output signal of a NOR state, in response to first and second input signals; a second block including a first AND-OR gate, the second block generating a second output signal of an OR or an AND state, the second block receiving the first and second input signals and the first output signal; a third block generating a third output signal of the NOR state, in response to a third input signal and the second output signal; a fourth block including a second AND-OR gate, the fourth block generating a fourth output signal of the OR or the AND state in response to the third input signal, the second output signal and the third output signal; and a fifth block including an inverter gate, the fifth block generating a fifth output signal in response to the fourth output signal.