Abstract: Some embodiments provide a multi-phase DC/DC switching converter in which each of the phases are controlled using a common comparator for comparing an output voltage of the switching converter and a reference voltage, with in some embodiments each of the phases including a bypass switch for coupling ends of an output inductor of the switching converter. Some embodiments provide a multi-phase DC/DC switching converter in which some of the phases are operated with clock signals having frequencies different than clock signals used for operating others of the phases. Some embodiments provide a multi-phase DC/DC switching converter in which some of the phases include inductors having inductances different than inductances for inductors of others of the phases.

Abstract: A reference voltage circuit (1) includes a PTAT voltage generation circuit (20) that generates a voltage with a positive temperature coefficient, a CTAT voltage generation circuit (10) that generates a voltage with a negative temperature coefficient, and a temperature characteristic adjustment circuit (30) that generates a voltage for adjusting temperature characteristics. The reference voltage circuit outputs a reference voltage (VOUT) formed by calculation based on the output of the PTAT voltage generation circuit, output of the CTAT voltage generation circuit, and output of the temperature characteristic adjustment circuit.

Abstract: An embodiment DC to DC conversion circuit comprises a DC to DC converter and a regulation circuit. The regulation circuit comprises a comparator configured to detect, during a discharge phase of the DC to DC converter, an overshoot period during which an output voltage of the DC to DC converter exceeds a target voltage, and a timer configured to measure a duration of the overshoot period.

Abstract: Circuits and methods that provide for fast power up and power down times in a multi-stage LDO regulator. In one embodiment, a multi-stage LDO regulator circuit includes, for each stage for which fast power up and/or power down times are desired, at least one transconductance amplifier coupled and configured to compare a primary reference voltage to one of a secondary reference voltage for the stage or an output voltage of the stage, and coupling and configuring the at least one transconductance amplifier to charge and/or discharge an associated capacitor to achieve a desired charge level within a specified time independently of the value of the associated capacitor. In general, the transconductance amplifiers of each stage are configured to charge and/or discharge an associated capacitor in synchronism with a voltage present on the primary reference voltage input.

Abstract: Disclosed is a voltage regulator, which makes a low dropout regulator stop working by controlling a sampling circuit of the low dropout regulator to break in a sleep mode, and makes an output voltage of the low dropout regulator follow an output voltage of a first bias voltage generating circuit by using a first MOS transistor connected between an voltage input end and an voltage output end of the low dropout regulator in a source follower structure, and is capable of controlling an output voltage of the whole voltage regulator by a generated bias voltage applied to the first bias voltage generating circuit by a first bias current source.

Abstract: A multi-level inverter having one or more banks, each bank containing a plurality of low voltage MOSFET transistors. A processor configured to switch the plurality of low voltage MOSFET transistors in each bank to switch at multiple times during each cycle.

Abstract: A power supply includes an inverter configured to direct current (DC) power into alternating current (AC) power, an impedance matching circuit configured to supply the AC power to a load; and a controller configured to adjust disposition of a powering period, in which the AC power is output, and a freewheeling period, in which the AC power is not output, to adjust a power amount of the power supplied to the load through the impedance matching circuit by the inverter.

Abstract: According to an aspect a low noise electronic voltage regulator comprises a regulating transistor operative to regulate an input DC voltage to provide a regulated DC output voltage, an error amplifier configured to generate an error signal based on a reference voltage and a feedback voltage, wherein the error amplifier receiving the feedback voltage through a feedback loop formed between the regulated DC output voltage and the feedback voltage, and a first amplifier in the feedback loop providing a gain of greater than unity from the regulated DC output voltage and the feedback voltage.

Abstract: The anti-windup circuit generally has a voltage clamping device in series with a current limiting device operatively connectable to the output current path of a feedback compensator; the feedback compensator being part of a switch-mode power supply (SMPS) having an input voltage source and a load and generating constrained control values required to generate control on-off actions for tight power regulation. The inclusion of the disclosed anti-windup circuit in an SMPS may lead to hardware based overvoltage protection, reduced overall size and faster response to load changes.

Abstract: A front-end module comprises a bias network including a current mirror, a junction temperature sensor, an n-bit analog-to-digital converter, an n-bit current source bank configured to automatically set reference current levels for one or more operating temperature regions, and a power amplifier. The bias network, junction temperature sensor, n-bit analog-to-digital converter, n-bit current source bank, and power amplifier are integrated on a first semiconductor die.

Abstract: A front-end module comprises a low-dropout (LDO) voltage regulator, a reference current generator, and a power amplifier. The LDO voltage regulator, reference current generator, and power amplifier are integrated on a first semiconductor die.

Abstract: Circuits and methods that compensate for the problems created by low-dropout regulator (LDO) leakage current, particularly when stressed. Embodiments include an improved LDO configured to provide a load current, and which includes a leakage current compensation circuit. The leakage current compensation circuit generates a compensating current that offsets the leakage current through the pass device of the LDO during conditions that induce such leakage. More specifically, the leakage current compensation circuit can replicate the leakage current of the pass device of the LDO and feed a compensating current back into the LDO from a current mirror circuit while drawing zero-power during normal use, when leakage current is absent. LDO circuits that include a leakage current compensation circuit are particularly useful as voltage sources for positive or negative charge pumps, but are also quite useful in applications requiring a regulated voltage output.

Abstract: A linear voltage regulator includes a voltage input and a voltage output. The linear voltage regulator includes a buffer having a voltage node, an input node, an output node and a control node and a power transistor having a control node coupled to the output node of the buffer, an input node coupled to the voltage input and an output node coupled to the voltage output. The linear voltage regulator includes a dropout detection module having a control node coupled to the control node of the power transistor, a voltage input node coupled to the voltage input, a voltage output node coupled to the voltage output and an output node. The linear voltage regulator includes a feedforward module having an input node coupled to the output node of the dropout detection module and an output node coupled to the control node of the buffer.

Abstract: Methods and apparatuses for controlling an apparatus comprising a controller integrated in a first slave device. In an example, the controller can detect a sensed current of the first slave device. The controller can receive a voltage signal associated with a second slave device connected to the first slave device. The controller can generate a correction current based on the sensed current of the first slave device and the voltage signal. The controller can modulate a pulse width modulation (PWM) signal received by the first slave device using the correction current. The controller can control a power converter using the modulated PWM signal.

Abstract: A voltage regulation circuit includes a switching output terminal, a high-side output transistor, a low-side output transistor, a high-side replica transistor, a low-side replica transistor, and a comparator circuit. The high-side output transistor is configured to drive the switching output terminal. The low-side output transistor is configured to drive the switching output terminal. The high-side replica transistor is coupled to the high-side output transistor. The low-side replica transistor is coupled to the high-side replica transistor and the low-side output transistor. The comparator circuit is coupled to the high-side replica transistor and the low-side replica transistor, and is configured to compare a signal received from both the high-side replica transistor and the low-side replica transistor to a ramp signal.

Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD protection device includes a primary ESD protection unit electrically connected to a first node and to a second node and configured to shunt current in response to an ESD pulse received between the first and second nodes and a secondary ESD protection unit electrically connected to the primary ESD protection unit and to the second node and configured to shunt current in response to the ESD pulse to keep an output voltage of the ESD protection device to be within a safe operating voltage range of a device to be protected. Other embodiments are also described.

Abstract: A reference voltage circuit is disclosed. In the reference voltage circuit, a comparator compares a reference voltage and a voltage of a capacitor, so as to output a comparison signal; a controller checks conditions of the reference voltage and the leakage current based on the comparison signal; when a voltage of the capacitor is reduced too quickly, the controller adjusts a switching frequency of a switch device to effectively maintain the voltage of the capacitor.

Abstract: A DLDO has a configuration that mitigates performance degradation associated with limit cycle oscillation (LCO). The DLDO comprises a clocked comparator, an array of power transistors, a digital controller and a clock pulsewidth reduction circuit. The digital controller comprises control logic configured to generate control signals that cause the power transistors to be turned ON or OFF in accordance with a preselected activation/deactivation control scheme. The clock pulsewidth reduction circuit receives an input clock signal having a first pulsewidth and generates the DLDO clock signal having the preselected pulsewidth that is narrower that the first pulsewidth, which is then delivered to the clock terminals of the clocked comparator and the digital controller. The narrower pulsewidth of the DLDO clock reduces the LCO mode to mitigate performance degradation caused by LCO.

Abstract: The invention relates to a circuit comprising a voltage reference (R) and a low-pass filter (F) electrically connected to the voltage reference (R). The filter (F) comprises a stage formed by a stage resistance (Re) electrically connected at a midpoint (M) to a stage capacitor (Ce), the stage resistance (Re) and the stage capacitor (Ce) at least partially defining a time constant of the filter and the midpoint (M) carrying the filtered reference voltage (V?ref). The circuit also comprises a transistor (T) and a control circuit (Cde) of the gate of the transistor (T) configured to bias the transistor (T) in conduction when the circuit (1) is turned on, the on-state resistance of the transistor (T) combining with the stage capacitor (Ce) to raise the filtered reference voltage (V?ref) with a settling time constant lower than the filter time constant.

Abstract: This disclosure describes systems, methods, and apparatus for reducing current imbalances between phases in a multi-phase converter as well as reducing instances of particular phases switching twice within a single pulse-width modulated cycle, or other time period. Phases that have not switched for a longest period of time can be compared to see if swapping their firing patterns would reduce current imbalances, and if so, then those firing patterns can be swapped.