Patents Examined by LaKaisha Jackson
  • Patent number: 12271216
    Abstract: Apparatus and methods for logarithmic current to voltage conversion are disclosed herein. In certain embodiments, a logarithmic current to voltage converter includes an input terminal that receives an input current, an output terminal that provides a logarithmic output voltage, a first field-effect transistor (FET) having a gate connected to the input terminal, a first bipolar transistor having a collector connected to the input terminal and an emitter connected to the output terminal, and a stacked transistor connected to the output terminal and to the first FET to form a feedback loop. For example, the stacked transistor can correspond to a second bipolar transistor having a collector connected to the output terminal and a base connected to the source of the first FET, or to a second FET having a drain connected to the output terminal and a gate connected to the source of the first FET.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: April 8, 2025
    Assignee: Analog Devices, Inc.
    Inventor: Petrus M. Stroet
  • Patent number: 12259743
    Abstract: A bandgap reference circuit includes a first current generator having first and second bipolar transistors for generating a first current that varies proportionally as a function of temperature. A second current generator includes a field effect transistor for generating a second current that varies inversely as a function of temperature. A trimming circuit includes a third bipolar transistor sized to match the first bipolar transistor, a third current generator having a second field effect transistor coupled to a collector and base of the third bipolar transistor to generate a third current based on a base current of the third bipolar transistor, and a trim control circuit configured to modify the second current by adding the third current to or subtracting the third current from the second current based on a trim control signal. A bandgap reference current is generated by summing the first current and the modified second current.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: March 25, 2025
    Assignee: NXP USA, Inc.
    Inventors: Guillaume Mouret, Yann Cargouet, Thierry Michel Alain Sicard
  • Patent number: 12261073
    Abstract: An electrostatic chuck including a workpiece support surface, clamping layer, heating layer, thermal control system, and sealing band is disclosed. The sealing band surrounds an outer perimeter of the electrostatic chuck including at least a portion of the workpiece surface. The sealing band has a width greater than about 3 millimeters (mm) up to about 10 mm. Plasma processing apparatuses and systems incorporating the electrostatic chuck are also provided.
    Type: Grant
    Filed: May 3, 2024
    Date of Patent: March 25, 2025
    Assignees: Beijing E-Town Semiconductor Technology Co., Ltd., Mattson Technology, Inc.
    Inventor: Maolin Long
  • Patent number: 12261518
    Abstract: Circuitry and methods for an improved gate driver circuit for power converters. The improved gate driver circuit substantially reduces propagation delay and transition losses in the floating-gate side of the gate driver circuit. One embodiment includes an inverter having an input configured to receive a state transition signal and an output configured to be coupled to a control input of a switching device. The inverter includes a first NFET having a control gate configured to be coupled to the state transition signal, a second NFET having a control gate coupled to the output of a reference circuit, and a PFET having a control gate configured to be coupled to the state transition signal, wherein the output of the inverter is a node between the conduction channels of the first NFET and the second NFET and the conduction channels of the first NFET, second NFET, and PFET are coupled in series.
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: March 25, 2025
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Gary Chunshien Wu
  • Patent number: 12253871
    Abstract: Described embodiments include a circuit for dampening overshoot in a voltage regulator. The circuit includes a first and second offset voltage circuits, each having an input coupled to an input voltage terminal. A first comparator has a first comparator input coupled to the first offset output, and a second comparator input coupled to a reference voltage terminal. A second comparator has a third comparator input coupled to an output of the second offset circuit, and a fourth comparator input coupled to a voltage regulator output. An OR gate has first and second logic inputs and a logic output. The first and second logic inputs are coupled to the outputs of the first and second comparators, respectively. A turn-off circuit has a turn-off input coupled to the logic output, and is configured to provide a turn-off signal at a turn-off output to stop current flow from the voltage regulator output.
    Type: Grant
    Filed: January 17, 2024
    Date of Patent: March 18, 2025
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Saurabh Rai, Venkateswarlu Ramaswamy Tiruvamattur, Ramakrishna Ankamreddi
  • Patent number: 12242292
    Abstract: Systems and methods as described herein may take a variety of forms. In an example, a circuit includes a first voltage stepdown module and a second voltage stepdown module. The first voltage stepdown module has a supply voltage and a first reference voltage as inputs, and an intermediate stepped down voltage as an output, the intermediate stepped down voltage being electrically coupled to a feedback input of the first voltage stepdown module. The second voltage stepdown module includes a low-dropout voltage regulator having the intermediate stepped down voltage and a second reference voltage as inputs and a target voltage as an output.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: March 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bindu Madhavi Kasina, Szu-Chun Tsao, Jaw-Juinn Horng
  • Patent number: 12233747
    Abstract: A power system, responsive to a detected change in an onboard charger or a generator, switches a converter from a first conversion setting, in which a first low voltage value of a medium-voltage bus port is converted to a first high voltage value of a high-voltage bus port, to a second conversion setting, in which a second low voltage value of the medium-voltage bus port is converted to the first high voltage value of the high-voltage bus port.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: February 25, 2025
    Assignee: FORD GLOBAL TECHNOLOGIES, LLC
    Inventors: Yantao Song, Baoming Ge, Lihua Chen, Serdar Hakki Yonak
  • Patent number: 12231058
    Abstract: A power conversion apparatus and a control method for a power conversion apparatus to reduce an amplitude of an output voltage of a converter when a grid is recovered from a fault, to ensure device safety. The power conversion apparatus includes a controller and a converter, and the controller is connected to the converter. The controller is configured to: after the output voltage of the converter is less than a first threshold, when the output voltage of the converter rises to be greater than a second threshold, reduce an active current output by the converter to a first current value, and reduce a reactive current output by the converter to a second current value, where the second threshold is greater than the first threshold.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: February 18, 2025
    Assignee: Huawei Digital Power Technologies Co., Ltd.
    Inventors: Congyuan Wang, Kai Xin, Zhangping Shao
  • Patent number: 12218592
    Abstract: A main comparator compares a feedback voltage VFB corresponding to an output voltage VOUT of a DC/DC converter with a reference voltage VREF and asserts a turn-on signal when the feedback voltage VFB falls below the reference voltage VREF. A timer circuit generates a turn-off signal S2 that transitions in level after an ON time TON proportional to (VOUT?VIN/VOUT has elapsed from assertion of the turn-on signal.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: February 4, 2025
    Assignee: ROHM CO., LTD
    Inventors: Akihiro Kawano, Hiroaki Ando
  • Patent number: 12218783
    Abstract: An integrated circuit with galvanic isolation is described herein. In accordance with one example, the circuit comprises a galvanic insulation barrier including a first isolation element configured to separate a first isolation domain from a second isolation domain and a first channel configured to transmit—in a first mode of operation and across the first isolation element—a logic signal from a first input in the first isolation domain to a first output in the second isolation domain. The first channel is further configured to transmit—in a second mode of operation and across the first isolation element—a serial data stream from the first input to a logic circuit in the second isolation domain, wherein the logic circuit is configured to receive—in the second mode of operation—the serial data stream and to store configuration information included in the serial data stream in a memory.
    Type: Grant
    Filed: October 13, 2022
    Date of Patent: February 4, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Andrea Morici, Thomas Ferianz
  • Patent number: 12218572
    Abstract: In an example, a system includes a differential amplifier having a first input terminal and a second input terminal, the differential amplifier configured to be coupled to a boost diode of a boost converter. The system also includes an input diode coupled to the first input terminal and the second input terminal. The system includes a pull-up circuit coupled to the input diode and configured to be coupled to the boost diode. The system also includes a pull-down circuit coupled to the pull-up circuit. The system includes a transistor coupled to the pull-up circuit and the pull-down circuit.
    Type: Grant
    Filed: July 6, 2022
    Date of Patent: February 4, 2025
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Aalok Dyuti Saha
  • Patent number: 12212232
    Abstract: An apparatus includes first and second pluralities of switches, a controller for controlling these switches, gate-drivers for driving switches from the first plurality of switches, and first and second terminals configured for coupling to corresponding first and second external circuits at corresponding first and second voltages. During operation, the controller causes the first plurality of switches to transition between states. These transitions result in the second voltage being maintained at a value that is a multiple of the first voltage. The controller also causes the second plurality of switches to transition between states. These transitions resulting in capacitors being coupled or decoupled from the second voltage. The gate drivers derive, from the capacitors, charge for causing a voltage that enables switches from the first plurality of switches to be driven.
    Type: Grant
    Filed: December 19, 2023
    Date of Patent: January 28, 2025
    Assignee: pSemi Corporation
    Inventors: David Giuliano, Gregory Szczeszynski, Raymond Barrett, Jr.
  • Patent number: 12206330
    Abstract: A method of DC-DC power conversion includes converting a DC link voltage to a DC output voltage for a load that is lower than the DC link voltage using a buck converter. The method includes controlling the buck converter in a normal switching mode in response to the DC link voltage being below a predetermined high threshold. The method also includes controlling the buck converter in a rate limited switching mode in response to the DC link voltage being at or above the predetermined high threshold.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: January 21, 2025
    Assignee: Hamilton Sundstrand Corporation
    Inventor: John Duward Sagona
  • Patent number: 12204353
    Abstract: A soft start module includes a power component, a current sensing component, a reference voltage generating circuit, and a constant current control circuit. The power component has a first terminal connected to a first node, a second terminal connected to an Output node, and a third terminal connected to a third node. The current sensing component has a fourth terminal connected to an input node and a fifth terminal connected to the first node. The reference voltage generating circuit has a seventh terminal connected to a fourth node and an eighth terminal connected to a ground node. The constant current control circuit has a ninth terminal connected directly or indirectly to the fifth terminal of the current sensing component, a tenth terminal connected the fourth node, and an eleventh terminal connected to the third node.
    Type: Grant
    Filed: October 5, 2022
    Date of Patent: January 21, 2025
    Assignee: Dartpoint Tech. Co., Ltd.
    Inventor: Chung-Hsin Hsieh
  • Patent number: 12199518
    Abstract: A flyback converter with improved over-voltage protection (OVP) functionality, which includes a primary winding arranged to receive an input voltage, a secondary winding coupled to the primary winding and connected to a rectifier circuit to generate DC output voltage, a primary side regulating controller, an auxiliary winding arranged to provide electric power to the primary side regulating controller, an external detection circuit connected between the auxiliary winding and the primary side regulating controller, an internal detection circuit arranged inside the primary side regulating controller and coupled to the external detection circuit by detecting the current value flowing through the external detection circuit and comparing it with a predetermined current value of the internal detection circuit to enable or disable an OVP circuit to protect the primary side regulating controller, and a switching device arranged to receive on/off signals generated for regulating current flowing through the primary win
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: January 14, 2025
    Assignee: Nanjing Greenchip Semiconductor Co., Ltd.
    Inventors: Szu-Han Chen, Wen-An Tsou
  • Patent number: 12199512
    Abstract: The present invention provides a controller, a switched-mode power supply and a method for controlling a switched-mode power supply. In response to a change of the switched-mode power supply from a continuous conduction mode to a discontinuous conduction mode, slope compensation is carried out with an output peak voltage raised by a compensating DC offset. Moreover, in response to a change of the switched-mode power supply from the discontinuous conduction mode to the continuous conduction mode, the compensating DC offset is subtracted from the peak voltage. In this way, an additional DC offset that would be introduced by a conventional slope compensation approach can be eliminated, maintaining a valley of a sampled feedback voltage constant both under steady load conditions and during load jumps.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: January 14, 2025
    Assignee: SHANGHAI BRIGHT POWER SEMICONDUCTOR CO., LTD.
    Inventor: Danzhu Lv
  • Patent number: 12191804
    Abstract: An inline DC feeder DC/DC voltage step-up harness for photovoltaic solar facilities includes a housing, a plurality of PV input connectors, at least one PV output connector. The housing incorporates a DC/DC converter, and has an input and an output. The plurality of PV input connectors are operatively connected to the housing at the input. The PV output connector is operatively connected to the housing at the output.
    Type: Grant
    Filed: October 10, 2023
    Date of Patent: January 7, 2025
    Assignee: Aderis Energy, LLC
    Inventors: Olee Joel Olsen, Jr., Adam Will Foodman, Bradley Allan Micallef
  • Patent number: 12184164
    Abstract: A multi-phase buck converter circuit is provided, including a power supply, a plurality of phase buck circuits, each phase buck circuit including an input terminal, an output terminal, and a second input terminal, with input terminals of the plurality coupled to the power supply, a plurality of inductors coupled to the output terminals of the plurality of phase buck circuits, the plurality of inductors providing an output voltage at an output of the multi-phase buck converter circuit, a detection controller coupled to the output terminals of the plurality of phase buck circuits, the detection controller configured to detect a fault in the plurality of phase buck circuits, and a drive circuit coupled to the detection controller and coupled to each second input terminal of the plurality of phase buck circuits. The drive circuit is configured to detect a faulty phase buck circuit and stop driving the faulty phase buck circuit.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: December 31, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yuliang Lu, Wenbo Zhou, Yuanhui Zheng, Limin Li
  • Patent number: 12176809
    Abstract: A drain and a source of an N-channel type FET included in a power feeding control apparatus are provided on an electric current path along which an electric current flows from a DC power supply to a load, the drain being a part of the FET into which the electric current is input and the source being a part of the FET from which the electric current is output. A driving circuit switches the FET off when a first determination circuit determines that a control voltage between a gate and the source of the FET is greater than or equal to a first threshold value, and a second determination circuit determines that a drain-source voltage between the drain and the source of the FET is greater than or equal to a second threshold value.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: December 24, 2024
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Hayaki Murata, Shunichi Sawano
  • Patent number: 12164324
    Abstract: In described examples, a circuit includes a first current mirror circuit. The first current mirror circuit is coupled to a power input terminal. A first stage is coupled to the first current mirror circuit, and a second stage is coupled to the first stage and to the first current mirror circuit. An amplifier is coupled to the first and second stages. The amplifier has first and second input terminals. The first input terminal is coupled to the first stage, and the second input terminal is coupled to the second stage. A second current mirror circuit is coupled to the first stage, the second stage and the amplifier.
    Type: Grant
    Filed: January 23, 2024
    Date of Patent: December 10, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sanjeev Praphulla Chandra Nyshadham, Subrato Roy