Patents Examined by LaKaisha Jackson
  • Patent number: 11949325
    Abstract: A power conversion device according to an embodiment may include: an output circuit configured to perform a power conversion operation of converting input power into an output power and outputting the output power; and a microcomputer configured to control the power conversion operation by the output circuit with power supplied from an internal power source of the output circuit, wherein the microcomputer outputs a status signal notifying whether the microcomputer is in a power shutdown permit period or a power shutdown inhibit period, and the output circuit includes a power supply stop circuit configured, when receiving the operation stop signal that instructs to stop the power conversion operation, to stop the power supply from the internal power source to the microcomputer on a condition where the status signal indicates that the microcomputer is in the power shutdown permit period.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: April 2, 2024
    Assignee: SANKEN ELECTRIC CO., LTD.
    Inventors: Junichi Takada, Toshihiro Nakano
  • Patent number: 11940828
    Abstract: A voltage tracking circuit is provided. The voltage tracking circuit includes first and second P-type transistors and a control circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The gate and the drain of the second P-type transistor are respectively coupled to the first voltage terminal and a second voltage terminal. The control circuit is coupled to the first and second voltage terminals and generates a control voltage according to the first voltage and the second voltage. The sources of the first and second P-type transistors are coupled to an output terminal of the voltage tracking circuit, and the output voltage is generated at the output terminal. In response to the second voltage being higher than the first voltage, the control circuit generates the control signal to turn off the first P-type transistor.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: March 26, 2024
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shao-Chang Huang, Yeh-Ning Jou, Ching-Ho Li, Kai-Chieh Hsu, Chun-Chih Chen, Chien-Wei Wang, Gong-Kai Lin, Li-Fan Chen
  • Patent number: 11929689
    Abstract: A power conversion device includes: a dead time application unit which applies a dead time to only one of a pair of pulse signals; a current polarity detection unit which detects a polarity of an output current; and a gate signal selection unit which, if the polarity of the output current is positive, selects the one pulse signal, to which the dead time has been applied, as a gate signal for a positive arm and selects the other pulse signal as a gate signal for a negative arm, and, if the polarity of the output current is negative, selects the one pulse signal, to which the dead time has been applied, as the gate signal for the negative arm and selects the other pulse signal as the gate signal for the positive arm.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: March 12, 2024
    Assignee: TOSHIBA MITSUBISHI-ELECTRIC INDUSTRIAL SYSTEMS CORPORATION
    Inventors: Ryoji Tsuruta, Hiroshi Masunaga, Tomohiro Tanaka
  • Patent number: 11923769
    Abstract: The control system includes a PFC circuit and a sampling control circuit, and the PFC circuit includes an inductor, a first power supply drive circuit, and a first bridge arm and a second bridge arm that are connected in parallel, and a first bridge arm midpoint is a serial connection point between a first upper bridge arm and a first lower bridge arm of the first bridge arm. The sampling control circuit is configured to control, based on voltages of two ends of an alternating current power supply, the first lower bridge arm to be turned on, so that the first power supply drive circuit starts charging. The sampling control circuit is further configured to: when charging duration of the first power supply drive circuit reaches first target duration, control the first lower bridge arm to be turned off, so that the first power supply drive circuit completes charging.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: March 5, 2024
    Assignee: HUAWEI DIGITAL POWER TECHNOLOGIES CO., LTD.
    Inventors: Ken Chin, Shanglin Mo, Yuanjun Liu
  • Patent number: 11914412
    Abstract: In described examples, a circuit includes a first current mirror circuit. The first current mirror circuit is coupled to a power input terminal. A first stage is coupled to the first current mirror circuit, and a second stage is coupled to the first stage and to the first current mirror circuit. An amplifier is coupled to the first and second stages. The amplifier has first and second input terminals. The first input terminal is coupled to the first stage, and the second input terminal is coupled to the second stage. A second current mirror circuit is coupled to the first stage, the second stage and the amplifier.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sanjeev Praphulla Chandra Nyshadham, Subrato Roy
  • Patent number: 11914410
    Abstract: Described embodiments include a circuit for controlling a voltage drop. The circuit includes a resistor coupled between an output voltage terminal and a reference voltage terminal. First, second and third switches each have respective first, second and third switch terminals. The respective second switch terminals are connected together and are coupled to the output voltage terminal. The respective third switch terminals are connected together and are coupled to the reference voltage terminal. A first transistor is coupled between a supply voltage terminal and the first switch. A second transistor is coupled between the supply voltage terminal and the second switch. A third transistor is coupled between the supply voltage terminal and the third switch. Control terminals of the first, second and third transistors are coupled to a gate control terminal.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Rajat Chauhan
  • Patent number: 11909331
    Abstract: A power supply includes an inverter configured to direct current (DC) power into alternating current (AC) power, an impedance matching circuit configured to supply the AC power to a load; and a controller configured to adjust disposition of a powering period, in which the AC power is output, and a freewheeling period, in which the AC power is not output, to adjust a power amount of the power supplied to the load through the impedance matching circuit by the inverter.
    Type: Grant
    Filed: March 17, 2023
    Date of Patent: February 20, 2024
    Assignee: EN2CORE TECHNOLOGY, INC.
    Inventors: Yeong-Hoon Sohn, Se-Hong Park, Sae-Hoon Uhm
  • Patent number: 11909351
    Abstract: An inline DC feeder DC/DC voltage step-up harness for photovoltaic solar facilities includes a housing, a plurality of PV input connectors, an at least one PV output connector. The housing incorporates a DC/DC converter, and has an input and an output. The plurality of PV input connectors are operatively connected to the housing at the input. The PV output connector is operatively connected to the housing at the output.
    Type: Grant
    Filed: October 7, 2022
    Date of Patent: February 20, 2024
    Assignee: ADERIS ENERGY, LLC
    Inventors: Olee Joel Olsen, Jr., Adam Will Foodman, Bradley Allan Micallef
  • Patent number: 11906995
    Abstract: A voltage regulator coupled between a first node and second node includes a first (full-power) regulator circuit and a second (low-power) regulator circuit. In a first mode: the first regulator circuit is activated (with the second regulator circuit inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is kept de-activated when the voltage at the first node is a ground voltage. In a second mode: the first regulator circuitry in is active (with the second regulator circuitry inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is inactive when the voltage at the first node is a ground voltage. In a third mode: the second regulator circuitry is active (with the first regulator circuitry inactive) irrespective of the voltage at the first node being at the battery voltage or the ground voltage.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: February 20, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Daniele Mangano, Francesco Clerici, Pasquale Butta'
  • Patent number: 11906999
    Abstract: Described embodiments include a circuit for dampening overshoot in a voltage regulator. The circuit includes a first and second offset voltage circuits, each having an input coupled to an input voltage terminal. A first comparator has a first comparator input coupled to the first offset output, and a second comparator input coupled to a reference voltage terminal. A second comparator has a third comparator input coupled to an output of the second offset circuit, and a fourth comparator input coupled to a voltage regulator output. An OR gate has first and second logic inputs and a logic output. The first and second logic inputs are coupled to the outputs of the first and second comparators, respectively. A turn-off circuit has a turn-off input coupled to the logic output, and is configured to provide a turn-off signal at a turn-off output to stop current flow from the voltage regulator output.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: February 20, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Saurabh Rai, Venkateswarlu Ramaswamy Tiruvamattur, Ramakrishna Ankamreddi
  • Patent number: 11899487
    Abstract: The present invention includes: a first current source, through which a first current is made to flow; a second current source, through which a second current set at a certain ratio to the first current is made to flow; a first current path, which includes a second resistor, a first resistor, and a first bipolar transistor that are connected to the first current source in a sequential manner, and through which the first current is made to flow; a second current path, which includes a third resistor and a 0th bipolar transistor that are connected to the second current source in a sequential manner, and through which the second current is made to flow; an operational amplifier, which controls current amounts of the first current and the second current by an output from an output end, and of which a positive input end is connected to a connection point between the second resistor and the first resistor, and of which a negative input end is connected to a connection point between the third resistor and the 0th bi
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: February 13, 2024
    Assignee: WILL SEMICONDUCTOR (SHANGHAI) CO. LTD.
    Inventor: Hiroyuki Kimura
  • Patent number: 11901818
    Abstract: An apparatus includes first and second pluralities of switches, a controller for controlling these switches, gate-drivers for driving switches from the first plurality of switches, and first and second terminals configured for coupling to corresponding first and second external circuits at corresponding first and second voltages. During operation, the controller causes the first plurality of switches to transition between states. These transitions result in the second voltage being maintained at a value that is a multiple of the first voltage. The controller also causes the second plurality of switches to transition between states. These transitions resulting in capacitors being coupled or decoupled from the second voltage. The gate drivers derive, from the capacitors, charge for causing a voltage that enables switches from the first plurality of switches to be driven.
    Type: Grant
    Filed: October 16, 2023
    Date of Patent: February 13, 2024
    Assignee: pSemi Corporation
    Inventors: David Giuliano, Gregory Szczeszynski, Raymond Barrett, Jr.
  • Patent number: 11899480
    Abstract: A voltage regulator circuit can include two feedback loops, such as to reduce or suppress an unwanted transient condition in an output voltage during transient conditions such as during startup or during load current demand transients. One of the two feedback loops can include a shunt device arranged to provide a temporary current pathway during the transient condition to change current provided to a load connected to an output of the voltage regulation circuit. In addition, or instead, the voltage regulator circuit can include an open-loop regulation circuit separate from a loop corresponding to the first error amplifier. The open-loop regulator circuit can operate in a lower-power mode as compared to a closed-loop regulator circuit. A portion or an entirety of the voltage regulator circuit can be implemented in an integrated circuit, such as monolithically.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: February 13, 2024
    Assignee: Analog Devices, Inc.
    Inventors: Colin Tse, James Lin
  • Patent number: 11899478
    Abstract: A low-power semiconductor device is provided. A retention transistor is provided between a control circuit and an output transistor. An output terminal of the control circuit is electrically connected to one of a source and a drain of the retention transistor, and the other of the source and the drain of the retention transistor is electrically connected to a gate of the output transistor. A node to which the other of the source and the drain of the retention transistor and the gate of the output transistor are electrically connected is a retention node. When the retention transistor is in an on state, a potential corresponding to a potential output from the control circuit is written to the retention node. Then, when the retention transistor is in an off state, the potential of the retention node is retained. Thus, a gate potential of the output transistor can be kept at a constant value even when the control circuit is off.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: February 13, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Keita Sato, Yuto Yakubo, Yoshiaki Oikawa, Shunpei Yamazaki
  • Patent number: 11885847
    Abstract: Proposed is an automatically testable short circuit breaker that includes: a pseudo short circuit signal driving circuit unit connected to opposite ends of a test button in a short circuit breaker; a pseudo short circuit signal recognition circuit unit which recognizes a short circuit detection signal and outputs a diagnosis signal; and a pseudo short circuit signal shut-off circuit unit which induces the short circuit detection signal to grounding so that the short circuit detection signal does not flow into the driving unit.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: January 30, 2024
    Inventor: Young Kil Choi
  • Patent number: 11881705
    Abstract: In a power distribution device, a current detection circuit detects a current value of a current flowing through a wire. When a switch is on, a microcomputer determines whether or not a predetermined condition is satisfied, based on the current value detected by the current detection circuit. If it is determined by the microcomputer that the predetermined condition is satisfied, a drive circuit turns off the switch.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: January 23, 2024
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Shunichi Sawano, Masayuki Kato
  • Patent number: 11876442
    Abstract: The present invention relates to advanced control for a DC-to-DC converter. For this purpose, in the determination of a controlled variable for the control of the DC-to-DC converter, the control dynamics are adjusted according to an electric current through the DC-to-DC converter. In particular, it is possible to determine the controlled variable from a combination of a first controlled variable of a voltage controller and a second controlled variable of a feedforward control. In particular, the control dynamics of the feedforward control can be adjusted according to the electric current through the DC-to-DC converter. By adjusting the control dynamics according to current, it is possible to minimize possible current ripple on the output side.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: January 16, 2024
    Assignee: Robert Bosch GmbH
    Inventor: Gholamabas Esteghlal
  • Patent number: 11870337
    Abstract: In an embodiment a current limiting circuit includes a circuit configured to detect when an input or output current of a DC to DC converter exceeds or falls below a threshold and a controller configured to store a first value representative of a level of an output voltage of the DC to DC converter in response to the input or output current exceeding or falling below a first threshold, store a second value representative of the level of the output voltage in response to the input or output current falling below a further threshold and modify a control signal based on the first and second values, wherein the control signal is modified based on the first and second values so that the control signal brings the output voltage to an intermediate voltage level between the level of the output voltage represented by the first value and the level of the output voltage represented by the second value.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: January 9, 2024
    Assignee: STMicroelectronics (Grand Ouest) SAS
    Inventor: Lionel Cimaz
  • Patent number: 11860656
    Abstract: A low-dropout voltage regulator is provided. The low-dropout voltage regulator includes a differential amplifier pair, a secondary amplification circuit that is self-stabilized, an output circuit, and a frequency compensation circuit. The secondary amplification circuit includes a first amplification transistor and a second amplification transistor. The first amplification transistor includes a first terminal, a second terminal, and a third terminal. The second amplification transistor includes a first terminal, a second terminal, and a third terminal. The second terminal of the first amplification transistor is electrically connected to the second terminal of the second amplification transistor to form an input terminal of the secondary amplification circuit to be connected to an output terminal of the differential amplifier pair.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: January 2, 2024
    Assignee: LITE-ON SINGAPORE PTE. LTD.
    Inventors: You-Fa Wang, Wei Shi, Darmayuda Imade
  • Patent number: 11855552
    Abstract: A multi-level inverter having one or more banks, each bank containing a plurality of low voltage MOSFET transistors. A processor configured to switch the plurality of low voltage MOSFET transistors in each bank to switch at multiple times during each cycle.
    Type: Grant
    Filed: January 26, 2023
    Date of Patent: December 26, 2023
    Assignee: Solaredge Technologies Ltd.
    Inventors: Ilan Yoscovich, Tzachi Glovinsky, Guy Sella, Yoav Galin