Patents Examined by Larry N. Anagnos
  • Patent number: 4845383
    Abstract: A voltage comparator circuit that is useful in A/D converters and D/A converters. The circuit comprises a comparison capacitor, a holding capacitor and input switching transistors. The holding capacitor holds the comparison voltage applied to it from the input switching transistors through the comparison capacitor. Therefore, the circuit can perform accurate voltage comparison even if the input voltages are sampled at a high sampling frequency.
    Type: Grant
    Filed: March 29, 1983
    Date of Patent: July 4, 1989
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Tetsuya Iida
  • Patent number: 4692637
    Abstract: A dynamic, multistage CMOS logic circuit is driven with a single source of clock pulses. The clock pulses operate odd-numbered stages. A static delay circuit provides clock pulses to even-numbered stages. The dynamic and static circuits are designed according to a discipline that guarantees the elimination of race conditions in the dynamic circuit despite the presence of uncontrollable variations in pullup and pulldown delays in the fabrication process.
    Type: Grant
    Filed: July 8, 1985
    Date of Patent: September 8, 1987
    Assignee: AT&T Bell Laboratories
    Inventor: Masakazu Shoji
  • Patent number: 4683383
    Abstract: A driver circuit for simultaneously setting up a plurality of output buffers of a 3-stage gate array into and out of a floating state using low control current. A buffer driver transistor is provided for each output buffer with the primary control path of that transistor introducing a control circuit to the respected output buffer. A common driver transistor has a primary current path which provides a control signal to the control electrodes of a plurality of buffer driver transistors. Clamp means are provided for discharging the conductor means to ground upon turn-off of the common driver transistor.
    Type: Grant
    Filed: July 19, 1984
    Date of Patent: July 28, 1987
    Assignee: Tandem Computers Incorporated
    Inventor: Hsienchin W. Wang
  • Patent number: 4680490
    Abstract: A solid state relay is responsive to a control signal and is used with an impedance load and a source of alternating electrical power. The solid state relay is used to connect and disconnect the load from the source of alternating electrical power. The solid state relay turns on in response to a control signal and to a substantially zero voltage crossing of the alternating electrical power of the source. The solid state relay turns off in response to the control signal and to a substantially zero current crossing of the alternating electrical power of the source.
    Type: Grant
    Filed: April 2, 1985
    Date of Patent: July 14, 1987
    Assignee: Gould Inc.
    Inventors: Richard H. Baker, Edward L. Maddox
  • Patent number: 4675553
    Abstract: Sequential logic circuits are implemented with inverter function logic gates. In each circuit, level shifted transistor means are utilized in place of the standard reference transistors found in ECL gate circuits so that the complement of at least one of the input signals may be included in the logical operation performed by the sequential logic circuit. The complementary clock signal is thus not required as a separate input. Sequential logic functions thus implemented have fewer gates, less complex clock drivers, consume less power and have shorter propagation delay.
    Type: Grant
    Filed: March 12, 1984
    Date of Patent: June 23, 1987
    Assignee: Amdahl Corporation
    Inventors: John E. Price, Larry W. De Clue
  • Patent number: 4673829
    Abstract: A charge pump for providing programming voltages to the word lines of a semiconductor memory array is disclosed. The charge pump, configured as a combination of enhancement and native MOS transistors, prevents DC current from flowing from the source of the programming voltage to ground through unselected word lines, and thereby permits the design of semiconductor programmable memory arrays having on-chip programming voltage generation, allowing for design of semiconductor programmable memory arrays which operate from a single voltage power supply.
    Type: Grant
    Filed: February 8, 1985
    Date of Patent: June 16, 1987
    Assignee: Seeq Technology, Inc.
    Inventor: Anil Gupta
  • Patent number: 4670675
    Abstract: A sense amplifier detecting a small current differential between a selected memory cell and a reference cell in a memory array includes a first pass transistor, a second pass transistor, a cross-coupled transistor arrangement and a differential amplifier. The cross-coupled transistor arrangement detect a small current differential between a bit sense current line and a bit sense reference current line. The difference current is amplified by the differential amplifier to produce an output data voltage indicative of the binary state of the selected memory cell.
    Type: Grant
    Filed: February 7, 1986
    Date of Patent: June 2, 1987
    Assignee: Advanced Micro Devices, Inc.
    Inventor: William J. Donoghue
  • Patent number: 4670676
    Abstract: A reset circuit resets an internal circuit (3) included in an electronic apparatus. The internal circuit generates a pulse signal indicating that the internal circuit is in an enabled state. This pulse signal is supplied to an inverter (63) through an integrating circuit comprising a resistor (61) and a capacitor (62), so that the pulse signal in the inverter is inverted in polarity to be supplied to one input terminal of an AND gate as a reset inhibit signal. To the other input terminal of the AND gate is supplied a reset signal generated based on transient phenomena at the time of turning on of the DC power source. If the AND gate is closed by the reset inhibit signal, the internal circuit does not receive the reset signal from the AND gate. Accordingly, the internal circuit in operation will never be reset if the reset signal is supplied thereto.
    Type: Grant
    Filed: January 15, 1985
    Date of Patent: June 2, 1987
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kazuharu Nishitani
  • Patent number: 4670670
    Abstract: The threshold voltage of a CMOS circuit is stabilized by a feedback loop which responds to variations in threshold voltage of a reference FET to provide a backbias voltage to readjust the threshold voltage of a second FET. The circuit is particularly useful to overcome threshold variations due to .gamma.-radiation.
    Type: Grant
    Filed: October 5, 1984
    Date of Patent: June 2, 1987
    Assignee: American Telephone and Telegraph Company AT&T Bell Laboratories
    Inventor: Masakazu Shoji
  • Patent number: 4659948
    Abstract: A single plane programmable logic array (PLA) using dynamic CMOS logic has switching transistors located at specific locations within a row-column matrix. The transistors within a column are series connected and have their gates common connected in rows. PMOS and NMOS control transistors conduct exclusively to connect output and input ends of the columns respectively to logic 1 or logic 0 in successive phases of a common clock. Control inputs are applied to specific rows. By applying data inputs to column input ends and interconnecting all the column output ends, the PLA is configured to function as a multiplexer. By setting the input end of columns to logic 0 and selectively interconnecting output ends of the columns, the PLA is configured to perform other combinational logic functions.
    Type: Grant
    Filed: July 18, 1983
    Date of Patent: April 21, 1987
    Assignee: Northern Telecom Limited
    Inventors: Stephen K. Sunter, Yachin Afek
  • Patent number: 4658160
    Abstract: A sense amplifier circuit for sensing the signals on input-output lines. Gate coupled and a.c. grounded pairs of transistors are used as sense amplifiers. Current mirror pairs of transistors are used as active loads. The gate coupled transistors provide d.c. level shifting without the need for additional circuitry, and the active current mirrors provide differential to single ended conversion of the I/O input-output signal which is then passed through one or more gain stages to drive an output buffer.
    Type: Grant
    Filed: October 1, 1985
    Date of Patent: April 14, 1987
    Assignee: Intel Corporation
    Inventor: Ian A. Young
  • Patent number: 4658159
    Abstract: A sense amplifier circuit for use in an MOS memory device, including bipolar sensing transistor, MOS load transistors connected to respective of the bipolar sensing transistors, and a constant current source, whereby high switching speed and high sensitivity are achieved.
    Type: Grant
    Filed: April 9, 1986
    Date of Patent: April 14, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Junichi Miyamoto
  • Patent number: 4658157
    Abstract: A voltage offset introduced in a differential amplifier stage by the addition of an offset current is rendered relatively constant by making the offset current a function of, and responsive to, the level of the differential input voltage applied to the differential amplifier stage.
    Type: Grant
    Filed: May 31, 1985
    Date of Patent: April 14, 1987
    Assignee: RCA Corporation
    Inventor: Michael J. McGowan
  • Patent number: 4656370
    Abstract: An integrated circuit (IC) of the invention is provided with a plural sets of power supply and ground lines within a package of the IC. Circuit elements, e.g., output buffers in the IC are divided into plural groups and each buffer group is coupled to the corresponding set of the power supply and ground lines. Each set of the power supply and ground lines is provided with independent wirings so that the magnitude of current change in each wiring and the value of each wiring inductance become small.
    Type: Grant
    Filed: July 24, 1984
    Date of Patent: April 7, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akira Kanuma
  • Patent number: 4652777
    Abstract: Large multi-input CMOS logic gates may be formed by a sequence of alternating CMOS NAND and NOR logic gates. The sequence of alternating gates may be compactly laid out in an integrated circuit to form arrays of functional AND or OR gates useful in PLAs. These arrays of CMOS gates consume low power and have response times suitable for integrated circuits.
    Type: Grant
    Filed: December 18, 1984
    Date of Patent: March 24, 1987
    Inventor: Ronald L. Cline
  • Patent number: 4651029
    Abstract: A decoder circuit used in a semiconductor memory device including a first and second voltage terminals; a NOR gate circuit including a plurality of inverter transistors for receiving address signals and connected in parallel between the first voltage terminal and a common output node, and a positive feedback transistor for positively feeding back a signal on the common output node and operatively connected between the second voltage terminal and the common output node; and a device, operatively connected between the second voltage terminal and the common output node, for conductively connecting the second voltage terminal to the node for a predetermined period in response to the changing of the address signals.
    Type: Grant
    Filed: April 3, 1986
    Date of Patent: March 17, 1987
    Assignee: Fujitsu Limited
    Inventor: Atsushi Oritani
  • Patent number: 4651028
    Abstract: An input circuit of MOS integrated circuit elements for a signal transmitting circuit having a first enhancement-mode MOS field-effect transistor, the gate thereof being connected to a power source and the drain thereof being connected to a first action signal, a second enhancement-mode MOS field-effect transistor, the drain thereof being connected to said power source, and a depletion-mode MOS field-effect transistor, the gate and source thereof being connected to each other, the source of said first enhancement-mode MOS field-effect transistor being connected to the gate of said second enhancement-mode MOS field-effect transistor, the source of said second enhancement-mode MOS field-effect transistor being connected to the drain of said depletion-mode MOS field-effect transistor, the source of the depletion-mode MOS field-effect transistor being connected to the signal transmitting circuit and a boost capacitor being connected between the gate of said second enhancement-mode MOS field-effect transistor and
    Type: Grant
    Filed: April 10, 1985
    Date of Patent: March 17, 1987
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Toshio Mimoto
  • Patent number: 4649301
    Abstract: A multiple input differential sense amplifier including a pair of signal inputs and comprising a bank of n-channel MOS transistors for receiving said multiple inputs for connection to one of said signal inputs. The other of said signal inputs can be provided with a fixed bias input, or a complementary input from a complementary bank of n-channel MOS transistors.
    Type: Grant
    Filed: January 7, 1985
    Date of Patent: March 10, 1987
    Assignee: Thomson Components-Mostek Corp.
    Inventor: Hiep Van Tran
  • Patent number: 4644190
    Abstract: A dynamic MOS-circuit comprising a bootstrap capacitor decoupled by an output transistor and wherein the bootstrap capacitor is discharged via a MOS-FET. The MOS-FET is connected as a constant current source. With the invention, a control voltage at an output MOS-FET is nearly double an operating voltage of the circuit.
    Type: Grant
    Filed: July 20, 1984
    Date of Patent: February 17, 1987
    Assignee: Siemens Aktiengesellschaft
    Inventors: Guenther Eberhard, Joachim Krause
  • Patent number: 4644196
    Abstract: An amplifier has a pair of common source transistors in which the sources are coupled together during a first mode of operation and isolated from each other during a second mode of operation. A current source provides current between a power supply terminal and these sources during the first mode and prevents current flow therebetween during the second mode. A pair of switchable loads act as loads for the common source transistors during the first mode and are switched off during the second mode.
    Type: Grant
    Filed: January 28, 1985
    Date of Patent: February 17, 1987
    Assignee: Motorola, Inc.
    Inventor: Stephen T. Flannagan