Abstract: A macrocell array is provided wherein a plurality of cells, each having a plurality of semiconductor devices interconnected for providing logic functions, are selectively interconnected to one another and to input/output pads by a plurality of horizontal and vertical routing channels in one or more metallization layers. An on-chip clock generator is provided within one of the cells and comprises a gate means responsive to an input signal and providing a delayed signal. An output means is coupled to the gate means and is responsive to the input signal and the delayed signal for generating a clock pulse. The gate means includes two or more serially connected sets of differentially connected transistors wherein the time between the input signal and the delayed signal is the summation of the propagation delays of the two or more serially connected sets of differentially connected transistors. External override signals allow for control of the clock pulse regardless of the state of the input signal.

Abstract: The invention provides a semiconductor integrated circuit, characteristics of which can be adjusted in accordance with storage data in a nonvolatile memory element. The semiconductor integrated circuit has a main semiconductor circuit having MOS transistors, and an adjusting circuit connected to the main semiconductor circuit so as to change the circuit characteristics of the main semiconductor circuit as needed. The adjusting circuit has MOS transistors and a plurality of fuse elements. The adjusting circuit causes a given fuse element to selectively disconnect in accordance with an input signal and generates at least one adjusting signal to adjust the circuit characteristics of the main semiconductor circuit.

Abstract: A TTL to CMOS input buffer has a CMOS inverter for receiving the TTL signal on its input. The inverter has a P channel transistor coupled between VDD and the output of the inverter, which has relatively low gain so that there is very little current flow through the inverter when the TTL signal is at low voltage logic high. A switch is coupled between VDD and the output of the inverter. The switch couples VDD to the output of the inverter in response to the TTL signal switching from a logic high to a logic low.

Abstract: A master-slave flip-flop device wherein the master segment employs function and load isolated outputs driven in parallel with cross-coupled latch transistors is described. Signal feed forward may also be provided from a similarly isolated output of the master segment to a device output gate which also receives the otherwise final output of the slave segment. The device is found to exhibit a minimized duration of the undesired metastable state of the master segment and to, thereby, enhance propagation speed in which a stable state is established.

Abstract: A transition detection circuit comprises an inverter circuit for inverting an input signal, an S-R flip-flop circuit receiving the input signal at one of its input terminals and the inverted input signal at the other input terminal, and having a time difference between the transitions of the signals at the output terminals; and a coincidence detection circuit receiving the output signals from the output terminals of the flip-flop circuit and generating a coincidence detection signal when the output signals are both at the same and specific logic level. The coincidence detection signal serves to represent a transition of logic level of the input signal.

Abstract: A bipolar OR logic circuit includes input diodes directly connected to a switching transistor. A first current source is coupled to the transistor's emitter and a load is directly connected to and between the collector and a voltage reference point. A second current source, connected to the transistor's base, sets the switching point of the transistor. The output is taken at the collector. A second bipolar transistor can be cross coupled to the first transistor to provide a voltage reference for the base of the first transistor and/or shift the logic level by taking the output at the emitter of the second transistor.

Abstract: A spare decoder provides for the substitution of a spare component for repair of a defective semiconductor chip. For example, a spare row or column of memory cells can be substituted for a defective row or column of a memory chip by fusing fusible links in the decoder. The present invention implements the decoder in CMOS technology. To minimize power consumption, means are included for preventing current flow in an unused spare without having to fuse a link.

Abstract: A compensation circuit for stabilization of a circuit node coupled to an integrated circuit substrate by a parasitic capacitance of a value C.sub.1 has a displacement current substantially equal to C.sub.1 dv/dt. A switching device having a gain beta can either supply a current to, or draw a current from, the circuit node substantially equal to C.sub.2 .beta. dv/dt which is greater than the displacement current thereby obviating oscillation of an integrated circuit output due to capacitive coupling of the substrate to sensitive circuit nodes.

Abstract: An interface circuit with MOS-type transistors for timing signal generators with two non-overlapping phases made up of two identical twin circuits, each having a final stage of the type including two transistors connected in series between the two terminals of a supply voltage generator and a bootstrap capacitor. Each of the two twin circuits includes a logic NOR circuit and a logic AND circuit which control, respectively, the charging and discharging of the capacitor through a suitable switching circuit connected to both terminals thereof. In each circuit, a memory circuit element is connected to the logic circuits. The memory circuit element is sensitive to the output signals of both twin circuits and enables the charging and discharging of the bootstrap capacitor at successive, logically produced time intervals which occur between the pulses of the output signals of both twin circuits.

Abstract: A variable-threshold-type differential signal receiver comprises a differential amplifier for comparing differential voltages of differential input signals with a predetermined threshold voltage so as to provide logical output signals. It further comprises an emitter follower and an impedance means, the output of the emitter follower being superimposed through the impedance means on one of the differential input signals, whereby the predetermined threshold voltage is variably controlled by controlling the input voltage of the first emitter follower.

Abstract: The invention provides a conversation device having a space key for instructing feeding of a printing tape without printing, a pulse oscillator for producing pulses of predetermined period upon depression of the space key, a counter for counting the pulses generated from the pulse oscillator, a one-shot multivibrator for producing a pulse to indicate that the count value has reached a predetermined value, a flip-flop which is set by the pulse from the one-shot multivibrator and allows the pulses from the pulse oscillator to be supplied to a motor driver for amplifying the pulses and which is reset when the predetermined number of pulses from the pulse oscillator is received and prohibits the supply of the pulse oscillator to the motor driver, and a pulse motor for feeding the printing tape without printing. Therefore, when the flip-flop is set, the motor driver causes the pulse motor to drive the printing tape for a predetermined length corresponding to a plurality of characters.

Abstract: A MIS semiconductor integrated circuit is one which contains an internal circuit. In the internal circuit, an externally supplied power source voltage supplied to a power source voltage terminal is supplied to the voltage input terminal of a voltage dropping circuit. The voltage at a voltage output terminal of the voltage dropping circuit is detected by a voltage detecting circuit containing an inverting circuit with a predetermined threshold voltage. The voltage dropping circuit is switch-controlled by applying the detected voltage to the control terminal thereof. The voltage output terminal of the voltage dropping circuit provides an internal power source voltage which is formed by dropping the externally supplied power source voltage. An internal circuit containing MOSFETs with an effective channel length of 1 .mu.m or less is driven by the internal power source voltage.

Abstract: A sense amplifier with two input control stages whose input voltages are equalized during a precharge cycle by a switching means.

Abstract: A logical circuit array is provided in which the AND and OR planes are folded together and all of the logic cell transistor gates are oriented in the same direction. The array comprises a plurality of AND rows R.sub.0 through R.sub.n, and means for precharging the AND rows to one logic level, e.g. V.sub.DD. An additional row R.sub.a is provided along with means for precharging the additional row to another logic level, e.g., ground. The array includes a plurality of data columns and an output column coupled to AND row R.sub.0. A plurality of logic cells is divided among AND rows R.sub.0 through R.sub.n-1. Each of the logic cells has an input terminal coupled to a data column, a first output terminal connected to the AND row with which the logic cell is associated, and a second output terminal connected to the next successive AND row in the array. A plurality of logic cells is associated with AND row R.sub.

Abstract: An improved TTL tristate device with reduced output capacitance incorporates an active discharge sequence of three elements including first and second active transistor elements (Q8, Q7) in an inversion coupling and a third passive element comprising a passive diode cluster (D3, D4, D5) coupled between the base of the second transistor element (Q7) and the enable gate. The passive diode cluster is operatively arranged for delivering base drive current to the base of the second transistor (Q7) when the enable gate (A) is at high potential for operation of the output device in the bistate mode. The passive diode cluster also operatively diverts base drive current away from the base of the second transistor (Q7) when the enable gate (A) is at low potential for operation of the output device in the high impedance third state with reduced output capacitance.

Abstract: Integrable frequency divider circuit, including a preamplifier in the form of a differential amplifier having a signal input for receiving signals to be processed, a reference input and two outputs, a frequency divider having divider stages including a first divider stage, each being in the form of identical series-connected flip-flop cells, the first divider stage having two inputs each being connected to a respective one of the two outputs of the differential amplifier for receiving the signals to be processed, an operational amplifier having an output directly connected to the reference input of the differential amplifier and having two inputs, two resistors each being connected between a respective one of the inputs of the operational amplifier and a respective one of the outputs of the differential amplifier, a capacitor connected between the inputs of the operational amplifier, and another capacitor connected between the output of the operational amplifier and reference potential.

Abstract: A CMOS logic circuit has MOSFETs of a first conductivity type in which each terminal is connected to a corresponding input terminal of the CMOS logic circuit, delay elements are inserted between the input terminals of the CMOS logic circuit and the gates of the MOSFETs of the first conductivity type, an output inverter is inserted between the remaining terminals of each of the MOSFETs of the first conductivity type and the output terminal of the CMOS logic circuit, and in which a MOSFET of a second conductivity type is inserted between the input terminal of the output inverter and a power source which is controlled by the output from the output inverter.

Abstract: A logic circuit of the I.sup.2 L, the ISL or the STL type having a signal input formed by the control electrode of an inverter transistor and plural signal outputs each coupled through a diode to a main electrode of the inverter transistor, this main electrode being connected to a supply line through a pull-up connection. The improvement relates to a further connection path comprising a Schottky diode and a resistor which bridges the main current path of the inverter transistor and which reduces the voltage swing at the main electrode.

Abstract: A high speed programmable prescaler has an input divider that divides an input stream of clock pulses by either 2 or upon command by 3. Connected to the input divider is a plurality of dividers that are electrically cascaded together from a first member to last member with each member of the plurality of dividers being capable of dividing the clock pulses applied to it by either 2 or upon command by 3. A prescaler selects either 2 or 3 for dividing the input stream of clock pulses so that number of clock pulses necessary to obtain an output pulse can be represented by the equation of 2.sup.N +M where N is the number of members of the plurality of dividers and M is the control number having a range of 0 to 2.sup.N -1.The critical path delays are minimized by using a flip-flop in the input divider to divide by 2 and then on command shifting the output of the flip-flop by 180.degree. to obtain the divide by 3 function.

Abstract: A network composed of a plurality of compensated current switch emitter-follower logic circuits and a generator of a current source control potential for the current sources of the logic circuits in which a symmetrical relationship between UP and DOWN logic levels is maintained at all times. A logic level tracking signal which tracks changes in the UP and DOWN logic levels in the logic circuits is produced by simulating at least a portion of one of the logic circuits. The logic level tracking signal is compared with the reference potential used for the logic levels, preferably ground, by a differential amplifier. The output of the differential amplifier is buffered and suitably level shifted to produce the current source control potential. The current source control potential is applied from the single control potential generator to each of the logic circuits. The control potential is also applied to the control input of a current source portion of the simulating circuit.