Abstract: An amplifier has a pair of common source transistors in which the sources are coupled together during a first mode of operation and isolated from each other during a second mode of operation. A current source provides current between a power supply terminal and these sources during the first mode and prevents current flow therebetween during the second mode. A pair of switchable loads act as loads for the common source transistors during the first mode and are switched off during the second mode.

Abstract: A decoder circuit for a static random access memory cell and which may be integrated in monolithic form using gallium arsenide field effect transistors. The circuit comprises a first logic NOR-gate P.sub.1 having (n+1) inputs on which the n coded memory address signals or their complements are received, and also the chip-enable selection signal SB. The gate P.sub.1 is connected by a load resistor R to a supply voltage V.sub.DD1. A second NOR-gate P.sub.2 receives the same inputs as the gate P.sub.1 and has as its load a transistor T.sub.0 the gate electrode of which receives the output of the gate P.sub.1 and the drain of which is connected to a power supply voltage V.sub.DD2 which is less than V.sub.DD1. The voltage V.sub.DD2 is also the supply voltage for the memory cell, and is set at the clipping value of the gate junctions of the constituent transistors of that cell. The output V.sub.S of the decoder is produced at the drains of the transistors forming the second NOR-gate P.sub.

Abstract: A static decoding circuit which may be utilized with E.sup.2 PROM arrays. The circuit utilizes predecoded address signals to generate signals to the word lines in read, program, erase and bulk erase modes. The circuit includes a low voltage to high voltage converter, CMOS switches and post decoders which include a p-channel device so that individual row lines may be erased as well as all the row lines. In the read mode, the selected word line goes to VCC and other go to zero. In the programming mode, the selected word line goes to VPP and the selected word line goes to zero and the unselected word lines go to VPP. In the bulk erase mode, all the word lines go to zero.

Abstract: This invention is effective in the speeding up of a decoder circuit and maintenance of output amplitude. The invention is characterized in that, in a decoder circuit composed of a multi-emitter transistor or at least one diode group in which the anodes of a plurality of diodes are connected, and a charge circuit having an output emitter follower transistor, the multi-emitter transistor or the forward voltage of the diodes are larger than the voltage between the base and the emitter of the output emitter follower transistor.

Abstract: A NOR gate consisting of a set of input FET's (Q1.sub.1 -Q1.sub.M) has a clamp (12/ Q2) that, when at least one of the input FET's is turned on, clamps the logical low level of the gate output voltage at a value which is largely constant irrespective of how many of the input FET's are conductive.

Abstract: A gallium arsenide NAND gate is connected between a power source and a ground potential. The gate is comprised of a load transistor of a normally-on type field effect transistor having an output terminal and a drain connected to the power source, a first driver transistor of a normally-off type field effect transistor having a gate electrode as a first input terminal and a source-to-drain current path series-connected to that of the load transistor, and a second driver transistor of two normally-off type field effect transistors having a common gate electrode for a second input terminal and source-to-drain current paths series-connected between the power source and the ground potential through the series-connected first driver transistor and load transistor. The normally-off type field effect transistors are parallel-connected to each other so as to equally constitute a single driver transistor as the second driver transistor.

Abstract: An integrated circuit chip in which clock pulses are distributed to a plurality of circuits includes a pattern of trimmable elements such as capacitors or transistors. The capacitors or transistors are trimmed during manufacture in order, for example, to adjust clock skew.

Abstract: A selective true or complement storage latch is disclosed which includes a data input switch having an input node connecting to a binary bit input source, a control input for accepting a first or second control state, a first data output node which is selectively connected to the data input node when the control input is in the first state and a second data output node which is selectively connected to the data input node when the control input is in the second state. There is also a first inverting gate having an input connected to the first data output of the data input switch and an output connected to a first storage node. The second inverting gate has an input connected to the first storage node and an output connected to the second storage node, the input of the second inverting gate being connected to the second output of the data input switch, the output of the second inverting gate being connected to the input of the first inverting gate.

Abstract: The present invention combines in either a logical AND function of N logical input signals, where N is a selected positive integer greater than or equal to 1, and provides programmably, either a direct AND output signal or a NAND output signal. The invention accomplishes this using a minimum number of components in the data path, between the logical input leads and logical output leads. A minimum of components in the data path reduces the propagation delay introduced by the circuit. The invention accomplishes this by providing two AND gates connected to the same set of N logical input signals. The output signal of one AND gate is inverted by an inverter with an enable/disable input lead. The output signal of the other AND gate is inverted twice by two inverters. The second inverter has an enable/disable input lead. Means are provided for exclusively enabling one or the other of the two inverters with an enable/disable input lead.

Abstract: A sense amplifier for a read only memory array which is formed from a multiplicity of NAND organized FET stacks. The sense amplifier compares the current sinking capacity of a selected bit line stack with that of a reference stackline, the difference being detected as a voltage shift in a differential stage. Pass FETs with gate electrodes biased in inverse proportion to the bit and reference line potentials are serially connected between the corresponding lines and reference nodes.

Abstract: A ratioless, zero d.c. power dissipating FET programmable logic array including a column boost capacitor for maintaining the columns of selected AND array transistors at approximately their precharged voltage while their associated OR array transistors are being evaluated.

Abstract: A BIMOS memory sense amplifier is provided having the low power dissipation and high noise immunity of CMOS devices while maintaining the high drive capability and switching speed associated with bipolar devices. A pair of differentially connected NPN transistors are coupled for receiving a first and a second bit current from the bit lines of a memory circuit. A MOS transistor circuit is coupled to the NPN transistors and is responsive to a differential output therefrom, for buffering two NPN push-pull output transistors.

Abstract: A double-balanced RF mixer circuit comprising two differential amplifiers each of which comprises a pair of transistors the emitters of which are connected in common and the bases of which are cross-coupled to provide common first and second base terminals to which an oscillator signal is applied. A radio frequency signal to be mixed is applied to a voltage-current converter comprising a pair of transistors connected as a balanced common-base circuit, the collectors of such transistors being coupled to the common-emitter terminals of the differential amplifiers. Such a mixer circuit provides improved intermodulation and noise behaviour as compared with mixers in which the voltage-current converter is a conventional differential amplifier.

Abstract: A gallium arsenide differential line receiver circuit has a first and second receiver means for receiving first and second differential input signal voltages. A pair of depletion transistor means for transforming the signal voltages into corresponding signal currents provides pull-up, and the depletion transistors have their gates operatively connected to the first and second receiver means. A pair of enhancement transistor means is operatively connected to the pair of depletion transistor means for outputting a gallium arsenide signal representation of the first and second differential input signal voltages. Positive feedback is provided for increasing the gain of the pair of enhancement transistors and is operatively connected to the pair of enhancement transistors. Shunting means is also provided for reducing hysteresis switching and is operatively connected to the pair of enhancement transistors.

Abstract: A power-on-reset circuit which functions with variations in process, temperature and supply voltage is provided. A differential comparator structure is provided which utilizes a differential pair of transistors and which has a substantially constant intrinsic offset voltage associated therewith. The intrinsic offset voltage is created by making one of the transistors of the differential pair of lightly doped depletion device and the other transistor a heavily doped depletion device. A second reference voltage is provided in response to a detected power-up voltage and is implemented with a voltage divider. Power-on-reset is provided in response to the relationship of the levels of the first and second reference voltages.

Abstract: A sensor amplifier of a differential amplifier type having an input selecting function. The sense amplifier has a pair of input circuit portions receiving a plurality of pairs of complementary input signals, one of the input circuit portions has a plurality of circuit units each generating the amplified output of one of a pair of complementary input signals in response to an address signal applied thereto, and the other input circuit portion comprising a plurality of circuit units each generating the amplified output of the other one of the pair of complementary input signals in response to the address signal applied thereto, The sense amplifier selects one of a plurality of pairs of complementary input signals, i.e., complementary signals on bit lines or on data buses, in accordance with the address signal and generates an output signal corresponding to a selected pair of complementary input signals.

Abstract: A field effect transistor driver circuit figured to have different rates of change of the output signal depending on fabrication mask designation of selected transistors to be either depletion or enhancement type devices.

Abstract: A flip-flop with a built-in enable function realized by the addition of two transistors between the trigger circuit and the output nodes of the flip-flop. This embodiment of the enable function causes no increase in power dissipation and may be used in any type of flip-flop.

Abstract: A bipolar transistor logic circuit has a hierarchical arrangement of pairs of bipolar transistors, each pair of transistors having their emitters connected together, and the bases of at least some pairs receiving a differential input to the logic circuit. The highest level has only one pair of transistors, with their emitters connected to a constant current source. A differential output is provided on two lines, at least the collectors of the lowest level being coupled selectively to the lines. The arrangement is required to be symmetrical. In an otherwise non-symmetrical arrangement, the arrangement is made symmetrical by including dummy pairs of transistors not receiving a differential input. In performing a logical operation, the differential output, and the collector potentials of each pair of transistors start to vary in the appropriate sense.

Abstract: Two MESFETS with the drain of one connected to the source of the other are driven in complementary fashion by a single inverter using a third MESFET and a voltage level shifter, in response to digital signals input to the inverter. Means for selectively disconnecting the power supply from the inverter to place the circuit in a low power, standby mode is provided. Depletion and enhancement mode MESFET configurations of the circuit are disclosed.