Patents Examined by Laura M. Holtzman
  • Patent number: 5449435
    Abstract: A method for forming a field emission device. A substrate is selectively patterned. An etch is performed to remove portions of the substrate to form protrusions. An oxidation is performed to the substrate that forms a first oxidized layer. A perpendicular etch is performed that removes portions of the first oxidized layer. A second oxidation is performed to the substrate that forms a second oxidized layer. A conductive or semiconductive layer is deposited onto the second oxidized layer. An etch is performed to remove a portion of the first oxidized layer and a portion of the second oxidized layer to expose the protuberance.
    Type: Grant
    Filed: November 2, 1992
    Date of Patent: September 12, 1995
    Assignee: Motorola, Inc.
    Inventors: Scott K. Ageno, Robert C. Kane
  • Patent number: 5328553
    Abstract: A planar surface (24) is obtained in a semiconductor device (10) having regions of differing material composition by means of a non-selective planarization process. The non-selective planarization process removes insulating material and conductive material at substantially the same rate. In one embodiment of the invention, stud vias (22) are formed by the removal of portions of a conductive layer (20) overlying the surface of an interlevel dielectric layer (16). Once the conductive layer (20) has been removed, the planarization process is continued and surface portions of the interlevel dielectric layer (16) are also removed. Upon completion of the process a planar surface (24) is formed having regions of conductive material and insulating material.
    Type: Grant
    Filed: February 2, 1993
    Date of Patent: July 12, 1994
    Assignee: Motorola Inc.
    Inventor: Stephen S. Poon
  • Patent number: 5322816
    Abstract: An interconnect layer (40) for interposing between two active circuit layers of a multi-chip module (50). The interconnect layer includes a layer of silicon (14) having first surface and second surfaces. A first layer of dielectric material (16) is disposed over the first surface and a second layer of dielectric material (12) disposed over the second surface. The interconnect layer includes at least one electrically conductive feedthrough (42) that is formed within an opening made through the layer of silicon. The opening has sidewalls (22) that are coated with a dielectric material (24) and an electrically conductive material for providing a topside contact (26). A second contact (28) is formed from the backside of the silicon layer after removing the substrate (10).
    Type: Grant
    Filed: January 19, 1993
    Date of Patent: June 21, 1994
    Assignee: Hughes Aircraft Company
    Inventor: Jerald F. Pinter
  • Patent number: 5320706
    Abstract: Polish slurry particles remaining on a semiconductor wafer after mechanical planarization are removed from the semiconductor wafer by polishing the wafer with a polishing pad while a mixture of deionized water and a surfactant is applied to the wafer and the pad.
    Type: Grant
    Filed: October 15, 1991
    Date of Patent: June 14, 1994
    Assignee: Texas Instruments Incorporated
    Inventor: Robert E. Blackwell
  • Patent number: 5318665
    Abstract: In etching a polysilicon film having a large step difference by means of the RIE method, use is made of a mixed gas of HBr and Ar (10 to 25%) or a mixed gas of HBr, Ar (5 to 25 %), and O.sub.2 (0.2 to 2%). With this arrangement, it is possible to eliminate the residuals in the step part, and etch the polysilicon film with high anisotropy with little etching of the underlying oxide film.
    Type: Grant
    Filed: April 7, 1992
    Date of Patent: June 7, 1994
    Assignee: NEC Corporation
    Inventor: Kirokazu Oikawa
  • Patent number: 5318663
    Abstract: A method of thinning SOI films for providing ultra-thin active device regions having excellent thickness uniformity and further having self-aligned isolation regions between the active device regions is disclosed. A substrate having an isolation layer formed thereon and further having a single crystal silicon layer formed upon the isolation layer is first provided. A thermal oxide layer is grown upon the silicon layer, patterned in desired regions corresponding to polish stop regions positioned between predetermined active device regions, and etched. The silicon layer is thereafter etched according to the patterned thermal oxide layer with a high selectivity etch, thereby creating grooves in the silicon layer.
    Type: Grant
    Filed: December 23, 1992
    Date of Patent: June 7, 1994
    Assignee: International Business Machines Corporation
    Inventors: Taqi N. Buti, Joseph F. Shepard
  • Patent number: 5312773
    Abstract: The disclosure relates to a method of forming a multilayer interconnection structure. The structure is a laminated body having a first conductive layer, a first insulating layer, a second conductive layer and a second insulating layer in an ascending order. In the method, firstly, a through-hole is formed on the laminated body so as to expose a surface of the first conductive layer and two opposed surfaces of the second conductive layer. Then, the two opposed surfaces of the second conductive layer is masked with a masking film, so as not to deposit thereon a conductive material which has a strong and selective adhesion on the first and second conductive layers. Then, the conductive material is deposited on the surface of the first conductive layer by a chemical vapor deposition method so as to fill a lower portion of the through-hole with the conductive material. Then, the masking film is removed so as to expose the two opposed surfaces of the second conductive layer.
    Type: Grant
    Filed: March 26, 1993
    Date of Patent: May 17, 1994
    Assignee: Sony Corporation
    Inventor: Naoki Nagashima
  • Patent number: 5308438
    Abstract: An apparatus and method for determining a selected endpoint in the polishing of layers on a workpiece in a chemical/mechanical polishing apparatus where the workpiece is rotated by a motor against a polishing pad. When a difficult to polish layer, i.e., one requiring a chemical change in a surface skin of the layer which skin is then abraded away by a mechanical process is removed from a more easy to polish surface, i.e., one that relies solely on mechanical abrasion and does not need to have a chemically converted skin thereon. The power required to maintain a set rotational speed in a motor rotating the workpiece significantly drops when the difficult to polish layer is removed. This current drop is used to detect the point at which the polishing must be stopped to avoid over polishing effects, i.e., dishing or thinning or removal of the more easily removed underlying material. Thus, an end point in the process can be established.
    Type: Grant
    Filed: January 30, 1992
    Date of Patent: May 3, 1994
    Assignee: International Business Machines Corporation
    Inventors: William J. Cote, John E. Cronin, William R. Hill, Cheryl A. Hoffman
  • Patent number: 5308415
    Abstract: A new method of forming contact or via openings is achieved. A photoresist layer is formed and patterned top of layers of insulating materials overlying a semiconductor substrate. An isotropic etch is performed etching both vertically and horizontally a portion of the insulating layers. The photoresist is pulled back via a pure isotropic etch. Since the resist is being etched threedimensionally, an overhang resist profile is formed at the top of the opening. The opening is completed by anisotropically etching the remainder of the contact or via opening. The overhang part of the resist is recessed back gradually during etching. The oxide is exposed gradually through and together with the resist recessing back. The step formed after the first isotropic etch will be exposed to the anisotropic etch and will be etched into a slope.
    Type: Grant
    Filed: December 31, 1992
    Date of Patent: May 3, 1994
    Assignee: Chartered Semiconductor Manufacturing PTE Ltd.
    Inventor: Erh-Nan Chou
  • Patent number: 5304510
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming a first insulating layer having a hole on a substrate, selectively forming a conductive layer in the hole, selectively forming a second insulating layer on the first insulating layer, patterning the second insulating layer, and forming an interconnection layer in an opening portion of the second insulating layer formed by patterning so as to be electrically connected to the conductive layer.
    Type: Grant
    Filed: November 25, 1992
    Date of Patent: April 19, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kyoichi Suguro, Haruo Okano
  • Patent number: 5304515
    Abstract: A method and apparatus for forming a dielectric thin film or pattern thereof is provided in which a positive or negative resist of a desired pattern is formed on various substrates including a semiconductor substrate by contact of the resist with a liquefied gas or super critical fluid of CO.sub.2, NH.sub.3 or the like. Alternatively, a thin film of an organic or inorganic compound dissolved or dispersed in an organic solvent which has been formed on substrate becomes substantially free of any organic matter or functional groups by contact with the liquefied gas or super critical fluid. Semiconductor devices of high performance and high reliability are ensured.
    Type: Grant
    Filed: August 7, 1992
    Date of Patent: April 19, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoyuki Morita, Takeshi Ishihara
  • Patent number: 5302536
    Abstract: A method of manufacturing a semiconductor device is set forth, in which a conductive layer (21) and a first insulating layer (22) are provided on a surface (2) of a semiconductor body (1). A conductor track (5) with an insulating top layer (6) is formed in these layers and the top layer (6) is formed in a first insulating layer (22) by means of a first etching treatment. Further, while masking with the top layer (6), the conductor track (5) is formed in the conductive layer (21) by means of a second etching treatment, after which the conductor track (5) is provided with a side edge insulation (7). The surface (2) and the conductor track (5) with its top layer (6) are covered by a second insulating layer (24), which is then subjected to a third anisotropic etching treatment until this layer (24) has been removed from the surface (2) and the top layer (6).
    Type: Grant
    Filed: November 16, 1990
    Date of Patent: April 12, 1994
    Assignee: U.S. Philips Corporation
    Inventor: Wilhelmus J. M. J. Josquin
  • Patent number: 5302233
    Abstract: In semiconductor manufacture a method of shaping the features of a semiconductor structure using chemical mechanical planarization (CMP) is provided. During CMP, a relatively soft polishing pad is utilized to conform to and contour a topography of the semiconductor structure. Another layer of a material such as a dielectric (e.g. TEOS based silicon dioxide) can then be deposited over the contoured topography without the inclusion of voids. The method of the invention is particularly suited to the formation of void free dielectric layers.
    Type: Grant
    Filed: March 19, 1993
    Date of Patent: April 12, 1994
    Assignee: Micron Semiconductor, Inc.
    Inventors: Sung C. Kim, Scott Meikle
  • Patent number: 5300188
    Abstract: The present invention provides a process for making a diamond layer having a substantially smooth upper surface and a predetermined thickness on a substrate. The process includes depositing a patterned polish stopping layer on a substrate to a predetermined thickness while leaving predetermined portions of the substrate exposed. A diamond layer is than deposited on the polish stopping layer and on the predetermined portions of the substrate left exposed. The diamond layer is polished down to the polish stopping layer thereby forming a diamond layer on the substrate having a thickness substantially equal to the predetermined thickness of the polish stopping layer. The polish is conducted by a method that includes the mechanical and/or chemical consumption of the diamond layer. The polish stopping layer is capable of substantially stopping the consumption of the diamond layer.
    Type: Grant
    Filed: November 13, 1992
    Date of Patent: April 5, 1994
    Assignee: Kobe Development Corp.
    Inventors: Alison J. Tessmer, David L. Dreifus
  • Patent number: 5298117
    Abstract: The linewidth in patterns produced by etching copper layers is more easily maintained using a specific etching medium. In particular, this medium includes aqueous hydrofluoric acid, copper chloride, and an additional chloride salt. The etching medium is also particularly useful for bilayer metal constructions such as the copper/titanium structure found in many multichip modules.
    Type: Grant
    Filed: July 19, 1993
    Date of Patent: March 29, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Karrie J. Hanson, Barry Miller, Barbara J. Sapjeta, Akshay V. Shah, Ken M. Takahashi
  • Patent number: 5296092
    Abstract: Disclosed is a method for planarizing the insulating layer formed on a semiconductor substrate without forming voids. An insulating layer is coated on a semiconductor substrate on which a metal wiring layer has been previously formed, and then a resist layer serving as a sacrificial layer is formed on the insulating layer. Etching the sacrificial layer provides a sacrificial residue on the insulating layer between portions of the metal wiring layer. After an upper portion of the insulating layer is istropically etched, the insulating layer and sacrificial residue are anisotropically etched. An insulating layer thus-obtained has a good profile so that a planarized insulating interlayer free of voids is obtained by an additional etch-back process using a second sacrificial layer. Consequently, a subsequent second metal wiring formation or lithography process can be easily carried out.
    Type: Grant
    Filed: April 30, 1992
    Date of Patent: March 22, 1994
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chunghoan Kim
  • Patent number: 5290733
    Abstract: A method of manufacturing semiconductor devices comprises steps of selectively forming metal leads on the surface a semiconductor substrate, and immersing the semiconductor substrate in a solution containing dissolved metal for depositing the dissolved metal on the surfaces of the metal leads. The solution contains dissolved metal having an ionization tendency equal to or smaller than ionization of the metal leads.
    Type: Grant
    Filed: August 6, 1992
    Date of Patent: March 1, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuo Hayasaka, Ayako Shimazaki, Haruo Okano
  • Patent number: 5288661
    Abstract: A semiconductor device according to the present invention comprises a substrate (4) in a periphery of which formed are elements isolating regions. A bonding pad (3) is formed above the elements isolating region with an isolation layer (7) provided therebetween. An underlying layer (12) having a buffering function is formed on a surface of the bonding pad and the semiconductor substrate. In case the elements isolating region is formed of LOCOS film (30), the underlying layer is formed between the bonding pad and the LOCOS film. In case the elements isolating region is of a field-shield structure (13, 14), the underlying layer (12) is formed by separating a part of a gate electrode layer (14) of the field shield into an island. The underlying layer buffers external force applied on the bonding pad in a bonding processing to prevent generation of cracks in the semiconductor layer.
    Type: Grant
    Filed: November 25, 1991
    Date of Patent: February 22, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shinichi Satoh, Hiroji Ozaki, Hiroshi Kimura, Wataru Wakamiya, Yoshinori Tanaka
  • Patent number: 5288666
    Abstract: A process for producing self-aligned titanium silicide. A silicon substrate is provided, silicon electrode and oxide insulator regions are formed on the substrate, and a titanium layer overlying the electrode and insulator regions is formed. The device is heated in an oxygen rich environment to form titanium silicide overlying the electrode regions and to form titanium oxide overlying the insulator regions and metal silicide.
    Type: Grant
    Filed: March 21, 1990
    Date of Patent: February 22, 1994
    Assignee: NCR Corporation
    Inventor: Steven S. Lee
  • Patent number: 5286678
    Abstract: The present invention generally involves the fabrication of semiconductor devices so as to reduce the active region to interconnect interface resistivity. Fabrication begins by forming active regions on a semiconductor device. Next, a titanium metal of approximately 900 .ANG. thickness is deposited on the semiconductor device. The semiconductor device is then annealed in a single step to form the interconnects.
    Type: Grant
    Filed: September 28, 1992
    Date of Patent: February 15, 1994
    Assignee: Intel Corporation
    Inventor: Rajiv Rastogi