Abstract: A method of filling features of a substrate to produce a planar patterned surface on said substrate is disclosed. The method includes the steps of: providing a substrate containing a pattern of features defined by a dielectric material; depositing thereon a layer of a conductor, whereby first portions of the conductive layer cover the dielectric material, second portions of the conductor layer fill the features, and third sidewall portions of the conductive layer connect the first and second portions; coating the substrate with a resist and patterning the resist with a resist pattern similar to said pattern of features; etching away all portions of the conductor layer, except the second portions filling the features, by etching under conditions such that lateral etching of the sidewall portions of the conductor layer is inhibited; and stripping the resist to result in a substrate having a substantially planar patterned surface. Planarized multichip modules and integrated circuits are also disclosed.

Abstract: A method and apparatus for forming a dielectric thin film or pattern thereof is provided in which a positive or negative resist of a desired pattern if formed on various substrates including a semiconductor substrate by contact of the resist with a liquefied gas or super critical fluid of CO.sub.2, NH.sub.3 or the like. Alternatively, a thin film of an organic or inorganic compound dissolved or dispersed in an organic solvent which has been formed on substrate becomes substantially free of any organic matter or functional groups by contact with the liquefied gas or super critical fluid. Semiconductor devices of high performance and high reliability are ensured.

Abstract: A compound semiconductor pellet has a zincblende crystal structure and is formed of a III-V compound semiconductor, such as GaAs. The major surface of the pellet and side surfaces thereof are both {100} planes. To obtain this type of pellet, [010] and [001] directions are selected as dicing directions. In the case of a crystal having a zincblende crystal structure, a direction which forms 45.degree. with reference to a cleavage plane of the crystal is selected as a dicing direction.

Abstract: Measurement of temperature - internal stress characteristics of an Al thin film formed on an Si substrate is performed. The amount of an impurity or impurities mixed in the thin f ilm can be obtained in accordance with the measured characteristics. A migration start temperature of Al atoms in the thin film in the characteristics obtained when the temperature is increased is fed back as information to the thin film formation step, thereby controlling an impurity amount in an atmosphere for forming the thin film.

Abstract: A process for fabricating a semiconductor device uses re-ionized water, such as carbonated water, to rinse the device while preventing microcorrosion of metal layers. In one embodiment of the invention, a semiconductor wafer is provided having an overlying metal layer and a patterned layer overlying the overlying metal layer. Selected portions of the overlying metal layer are etched using the patterned layer as an etch mask. The patterned layer is removed by immersing the device in an organic solution without affecting the remaining metal layer. The device is then rinsed in a reservoir of re-ionized water to remove the organic solution from the device while preventing microcorrosion of the remaining metal layer.

Abstract: A fine pattern formation using an electron beam induced resist, and use of the resist in making semiconductor devices are disclosed. Collimated electron beam is irradiated and scanned along a desired pattern on a layer on which a resist layer of a desired pattern is deposited under an atmosphere containing a starting material layer for the resist. The resist thus deposited is partially removed by reactive ion etching to remove the skirt like portion of the resist layer, or totally removed by reactive ion etching during or after processing by using the resist layer as a processing mask. Since the resist layer width is determined by a diameter of the collimated electron beam, line width of less than hundred .ANG. can be directly drawn. There are also disclosed processes using the resist layer in manufacturing semiconductor devices.

Abstract: A method of planarizing SiO.sub.2 containing dielectric in semiconductor wafer processing comprising: a) providing a layer of undoped SiO.sub.2 atop a wafer; b) depositing a layer of borophosphosilicate glass atop the layer of undoped SiO.sub.2 ; and c) chemical mechanical polishing the borophosphosilicate glass layer selectively relative to the underlying layer of undoped SiO.sub.2 layer and using the layer of undoped SiO.sub.2 as an effective chemical mechanical polishing end-point etch stop to prevent further etching of the borophosphosilicate glass and produce a substantially planar upper wafer surface of dielectric.

Abstract: Methods of forming electrically and/or thermally conductive feedthroughs in silicon wafers by etching a patterned silicon wafer, and formation of multichip modules utilizing silicon wafers having feedthroughs, are disclosed.

Abstract: A process for layering a low reflectivity metal layer on a semiconductor wafer for decreasing the optical reflectivity and increasing the optical absorptivity of the metal layer for laser processing. The process includes: depositing a metal layer, such as aluminum, over a substrate, roughening the surface of the metal layer by chemical mechanical planarization (CMP) while injecting a silicon oxide slurry over the surface and then laser processing the metal. The roughened metal surface has an increased surface area and irregular surface features that help absorb incident laser radiation with less reflectance.

Abstract: A diffusion barrier which reduces the diffusion of a copper feature into an oxygen containing polymer is provided by a copper metal alloy. The diffusion barrier is fabricated by coating a metal on a copper feature, heating the metal and copper feature to form an alloy of the copper feature and the metal, etching the non-alloyed metal which covers the alloy, and depositing an oxygen containing polymer on the alloy. Preferably the metal is aluminum and a copper aluminum alloy diffusion barrier is at least 300 angstroms thick and contains at least 8 percent aluminum on the surface in contact with the polymer.

Abstract: The base of solder bumps is preserved by converting the under-bump metallurgy between the solder bump and contact pad into an intermetallic of the solder and the solderable component of the under-bump metallurgy prior to etching the under-bump metallurgy. The intermetallic is resistant to etchants which are used to etch the under-bump metallurgy between the contact pads. Accordingly, minimal undercutting of the solder bumps is produced, and the base size is preserved. The solder may be plated on the under-bump metallurgy over the contact pad through a patterned solder dam layer having a solder accumulation region thereon. The solder dam is preferably a thin film layer which may be accurately aligned to the underlying contact pad to confine the wetting of the molten solder during reflow. Misalignment between the solder bump and contact pad is thereby reduced. The solder bumps so formed include an intermetallic layer which extends beyond the bump to form a lip around the base of the bump.

Abstract: Self-aligned and/or isolated contacts are formed in a semiconductor device, while simultaneously providing device planarization. In one form, an imagable material is deposited directly on a substrate material. The imagable material is patterned to form a sacrifical plug on a portion of the substrate material. A substantially planar insulating layer is then deposited overlying the substrate material. The plug formed of the imagable material is then removed, thereby exposing a portion of the substrate material and defining a contact opening. A conductive layer is deposited and patterned to complete formation of a contact.

Abstract: Semiconductor devices having a low density of dislocation defects can be formed of epitaxial layers grown on defective or misfit substrates by making the thickness of the epitaxial layer sufficiently large in comparison to the maximum lateral dimension. With sufficient thickness, threading dislocations arising from the interface will exit the sides of the epitaxial structure and not reach the upper surface. Using this approach, one can fabricate integral gallium arsenide on silicon optoelectronic devices and parallel processing circuits. One can also improve the yield of lasers and photodetectors.

Abstract: A method for forming multilayer bump contacts for use in flip-chip bump bonding and the like. The method comprises applying a base layer to a substrate and then applying a malleable conductive layer to the base layer. In a first embodiment, individual bump contacts are formed by removing portions of the base layer and malleable layer such that a plurality of bump contacts are formed. In a second embodiment a photoresist and etching process is used. The need to precisely align a mark to define the position of the malleable layer relative to the base layer is eliminated since the positions of the malleable layer and the base layer are defined simultaneously in both embodiments. Thus, the number of process steps is reduced, yield is increased, and alignment accuracy is improved.

Abstract: A method for filling VLSI high aspect ratio vias and lines in VLSI interconnection structures, with a low resistivity metal at temperatures below 400.degree. C. A low melting point alloy of a desired low resistivity metal is deposited into the high aspect ratio vias or lines. The alloy is then purified in place by bringing the alloying element to the surface of the deposited alloy and removing the element from said surface thereby leaving the low resistivity metal in the interconnection structure. In one embodiment, the alloy is purified by using a low temperature oxidation process to allow the alloying element to diffuse to the surface of the deposited alloy where a surface oxide is formed. The surface oxide is then removed by chemical etching or by chemical mechanical polishing. In a second embodiment, a continuous exposure to a plasma etching or reactive ion etching will steadily remove the alloying element from the surface of the deposited alloy.

Abstract: A semiconductor element is formed in a semiconductor substrate. An electrode wiring pattern which is connected to the active region and contains aluminum as the main component is formed on the main surface of said semiconductor substrate. A metal bump is formed on the electrode wiring pattern. The metal bump contains zinc of 1 to 10% in mass percentage in addition to at least one element selected from a group consisting of tin, lead and aluminum a second metal bump is formed having a lower melting point than that of first bump. The second bump contains lead, tin and at least one of silver and copper.

Abstract: In a semiconductor device, an inter-level insulating film is formed at solid crossing points between upper level interconnections and lower-level interconnections, excepting via hole portions. This means that mechanical support between interconnection levels is given by solid crossing points between interconnections. For this, a semiconductor device having high durabilities against thermal and mechanical impacts can be obtained.Further, since inter-level regions other than the solid crossing points are made vacant to form a cavity, coupling capacity can be reduced to 1/3 to 1/2 of an ordinary multilevel interconnections wherein inter-level regions are fully filled with an inter-level insulating film.

Abstract: A polysilicon deposition process is disclosed for forming a doped polysilicon layer over a stepped surface on a semiconductor wafer having the deposition characteristics and resulting profile of an undoped polysilicon layer which comprises: depositing doped polysilicon on the stepped surface, depositing undoped polysilicon over the doped polysilicon, repeating the doped and undoped depositions cyclically until the desired amount of polysilicon has been deposited, and then annealing the deposited polysilicon to uniformly distribute the dopant throughout the entire deposited polysilicon layer.

Abstract: Low resistance contacts for establishing an electrical pathway to an integrated surface substrate are provided. The pathway is formed by the connection of a p+ doped channel stop region with a p+ doped extrinsic layer. P+ doped polysilicon contacts are positioned on the substrate surface. In one embodiment, a metal silicide layer connects the polysilicon contacts and overlies the p+ doped extrinsic layer.

Abstract: A method of forming a conductive pattern for a semiconductor device free from troubles attributable current leakage and having high reliability. Contact holes are formed in an insulating film formed over a semiconductor substrate by selectively etching portions of the insulating film corresponding to the contact holes so that portions of the semiconductor substrate corresponding to the contact holes are etched in recesses. Insulating side walls are formed on the side surface of the contact holes so as to reach the bottom of the recesses, the contact holes are filled up with a conductive substance by a selective CVD process, a conductive film is formed over the entire surface of insulating film so as to be connected to the conductive substance filling up the contact holes, and then portions of the conductive film are removed to form a conductive pattern.