Patents Examined by Laura M Schillinger
  • Methods for fabricating metal-oxide-semiconductor field effect transistors using gate sidewall spacers
    Patent number: 7122417
    Abstract: Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is fabricated by forming gate spacers on both sidewalls of a gate pattern in a semiconductor substrate including first and second regions. Then, a first impurity region is formed in the semiconductor substrate at the first region, and the gate spacer exposed at the first region is removed. A second impurity region is formed in the semiconductor substrate at the first region. A third impurity region is formed at the semiconductor substrate in the second region, and the gate spacer exposed at the second region is removed. A fourth impurity region is formed in the semiconductor substrate at the second region. The first and third impurity regions are formed deeper than the second and fourth impurity regions.
    Type: Grant
    Filed: February 10, 2004
    Date of Patent: October 17, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dong-Soo Chang
  • Fabrication method of semiconductor circuit device
    Patent number: 7122447
    Abstract: When a semiconductor wafer is formed to be thin, steps need to be taken to prevent warping of the wafer. For this purpose, a protective tape is affixed to a surface of the semiconductor wafer, and a back side of the semiconductor wafer is then ground to a predetermined thickness. A die bonding film is affixed to the back side of the semiconductor wafer, and a dicing tape is affixed on the die bonding film. The dicing tape that is affixed to the semiconductor wafer is held by a holding jig. The protective tape is peeled off from the wafer surface, and the die bonding film is heated to improve the adherence between the semiconductor wafer and the die bonding film. The semiconductor wafer is subjected to dicing for separation into individual semiconductor chips. The semiconductor chips are then die-bonded in a predetermined number onto a wiring substrate to fabricate a semiconductor device.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: October 17, 2006
    Assignee: Renesas Technology Corp.
    Inventor: Yoshiyuki Abe
  • Deposition of carbon and nitrogen doped poly silicon films, and retarded boron diffusion and improved poly depletion
    Patent number: 7119016
    Abstract: A compound that includes at least Si, N and C in any combination, such as compounds of formula (R—NH)4-nSiXn wherein R is an alkyl group (which may be the same or different), n is 1, 2 or 3, and X is H or halogen (such as, e.g., bis-tertiary butyl amino silane (BTBAS)), may be mixed with silane or a silane derivative to produce a film. A polysilicon silicon film may be grown by mixing silane (SiH4) or a silane derviative and a compound including Si, N and C, such as BTBAS. Films controllably doped with carbon and/or nitrogen (such as layered films) may be grown by varying the reagents and conditions.
    Type: Grant
    Filed: October 15, 2003
    Date of Patent: October 10, 2006
    Assignees: International Business Machines Corporation, Applied Materials, Inc.
    Inventors: Ashima B. Chakravarti, Anita Madan, Woo-Hyeong Lee, Gregory Wayne Dibello, Ramaseshan Suryanarayanan Iyer
  • Method of depositing a material layer
    Patent number: 7115516
    Abstract: A method of layer formation on a substrate with high aspect ratio features is disclosed. The layer is formed from a gas mixture comprising one or more process gases and one or more etch species. The one or more process gases react to deposit a material layer on the substrate. In conjunction with the material layer deposition, the etch species selectively remove portions of the deposited material layer adjacent to high aspect ratio feature openings, filling such features in a void-free and/or seam-free manner. The material layer may be deposited on the substrate using physical vapor deposition (PVD) and/or chemical vapor deposition (CVD) techniques.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: October 3, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Liang-Yuh Chen, Daniel A. Carl, Israel Beinglass
  • Method of atomic layer deposition on plural semiconductor substrates simultaneously
    Patent number: 7112544
    Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: September 26, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Trung Tri Doan, Lyle D. Breiner, Er-Xuan Ping, Lingyi A. Zheng
  • Methods of forming assemblies comprising silicon-doped aluminum oxide
    Patent number: 7112543
    Abstract: The invention encompasses a method of forming a silicon-doped aluminum oxide. Aluminum oxide and silicon monoxide are co-evaporated. Subsequently, at least some of the evaporated aluminum oxide and silicon monoxide is deposited on a substrate to form the silicon-doped aluminum oxide on the substrate. The invention also encompasses methods of forming transistors and flash memory devices.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: September 26, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Ki Y. Ahn, Leonard Forbes
  • Methods of fabricating a composite carbon nanotube thermal interface device
    Patent number: 7112472
    Abstract: Embodiments of a composite carbon nanotube structure comprising a number of carbon nanotubes disposed in a matrix comprised of a metal or a metal oxide. The composite carbon nanotube structures may be used as a thermal interface device in a packaged integrated circuit device.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: September 26, 2006
    Assignee: Intel Corporation
    Inventor: Valery M. Dubin
  • Integrated nitride-based acoustic wave devices and methods of fabricating integrated nitride-based acoustic wave devices
    Patent number: 7112860
    Abstract: A monolithic electronic device includes a substrate, a semi-insulating, piezoelectric Group III-nitride epitaxial layer formed on the substrate, a pair of input and output interdigital transducers forming a surface acoustic wave device on the epitaxial layer and at least one electronic device (such as a HEMT, MESFET, JFET, MOSFET, photodiode, LED or the like) formed on the substrate. Isolation means are disclosed to electrically and acoustically isolate the electronic device from the SAW device and vice versa. In some embodiments, a trench is formed between the SAW device and the electronic device. Ion implantation is also disclosed to form a semi-insulating Group III-nitride epitaxial layer on which the SAW device may be fabricated. Absorbing and/or reflecting elements adjacent the interdigital transducers reduce unwanted reflections that may interfere with the operation of the SAW device.
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: September 26, 2006
    Assignee: Cree, Inc.
    Inventor: Adam William Saxler
  • Integrated circuit memory with offset capacitor
    Patent number: 7109545
    Abstract: A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined pattern relative to one another to provide a maximum amount of capacitance per semiconductor die area.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: September 19, 2006
    Assignee: Micron Technology, Inc.
    Inventors: R. Jacob Baker, Kurt D. Beigel
  • Single electron devices formed by laser thermal annealing
    Patent number: 7105425
    Abstract: A semiconductor device with a superlattice and method of making same includes forming a layer of amorphous silicon over a substrate, and forming a layer of nanocrystals by laser thermal annealing the layer of amorphous silicon. A gate dielectric is formed between the layer of amorphous silicon and the substrate. A dielectric layer is formed on the layer of amorphous silicon. The steps of forming the layer of amorphous silicon and forming the dielectric layer can be repeated. The thickness of the dielectric layer is between about 25 to 40 angstroms, and the thickness of the amorphous silicon layer is between about 30 to 50 angstroms. The average diameter of the nanocrystals is less than 40 angstroms.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: September 12, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Zoran Krivokapic
  • Rugged metal electrodes for metal-insulator-metal capacitors
    Patent number: 7105405
    Abstract: Thin film metal-insulator-metal capacitors having enhanced surface area are formed by a substituting metal for silicon in a preformed electrode geometry. The resulting metal structures are advantageous for high-density DRAM applications since they have good conductivity, enhanced surface area and are compatible with capacitor dielectric materials having high dielectric constant.
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: September 12, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Klaus F. Schuegraf
  • Semiconductor device and manufacturing method for the same
    Patent number: 7105387
    Abstract: A semiconductor device of the present invention has a pn-repeating structure that a structure in which a p-type impurity region (4) and an n-type drift region (3) are aligned side by side is repeated twice or more, and a low concentration region which is either p-type impurity region (4) or n-type drift region (3) located at the outermost portion of this pn-repeating structure has the lowest impurity concentration or has the least generally effective charge amount among all the p-type impurity regions (4) and n-type drift regions (3) forming the pn-repeating structure.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: September 12, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tadaharu Minato, Tetsuya Nitta
  • Silicon on insulator field effect transistor with heterojunction gate
    Patent number: 7105421
    Abstract: A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with a first impurity to increase free carrier conductivity of a first type. The source region and the drain region are heavily dopes with the first impurity. A gate and a back gate are positioned along the side of the channel region and extending from the source region and is implanted with a second semiconductor with an energy gap greater than silicon and is implanted with an impurity to increase free carrier flow of a second type.
    Type: Grant
    Filed: April 29, 2004
    Date of Patent: September 12, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Qi Xiang, Matthew S. Buynoski
  • Means for forming SOI
    Patent number: 7101772
    Abstract: A method for forming a SOI structure in which porous silicon is sealed and an epitaxial layer is grown thereover, followed by implantation of oxygen and annealing.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: September 5, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Theodore W. Houston, Keith A. Joyner
  • Methods for producing full-color organic electroluminescent devices
    Patent number: 7098060
    Abstract: The invention provides methods for the production of full-color, subpixellated organic electroluminescent (EL) devices. Substrates used in the methods of the invention for production of EL devices comprise wells wherein the walls of the wells do not require surface treatment prior to deposition of electroluminescent material. Also provided are EL devices produced by the methods described herein.
    Type: Grant
    Filed: August 18, 2003
    Date of Patent: August 29, 2006
    Assignee: E.I. du Pont de Nemours and Company
    Inventors: Gang Yu, Gordana Srdanov, Matthew Stainer, Jeffrey Glenn Innocenzo, Runguang Sun
  • Manufacture of electronic devices comprising thin-film transistors
    Patent number: 7094654
    Abstract: A method of manufacturing an electronic device including a thin film transistor comprises forming a semiconductor film over an insulating substrate; depositing a first masking layer over the semiconductor film and removing portions of it to form a plurality of holes through it that extend substantially perpendicularly from its upper to its lower surface; patterning the first masking layer in a first pattern; depositing a second masking layer over the first masking layer; patterning the second masking layer to define a second pattern that lies within the area of the first pattern; and implanting the semiconductor film using at least the first masking layer as an implantation mask.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: August 22, 2006
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Frank W. Rohlfing
  • Planarizing sacrificial oxide to improve gate critical dimension in semiconductor devices
    Patent number: 7091068
    Abstract: A method of manufacturing a semiconductor device may include forming a fin structure on an insulator and depositing a gate material over the fin structure. The method may also include forming a sacrificial material over the gate material and planarizing the sacrificial material. An antireflective coating may be deposited on the planarized sacrificial material. A gate structure may then be formed by etching the gate material.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: August 15, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shibly S. Ahmed, Cyrus E. Tabery, Bin Yu
  • Open pattern inductor
    Patent number: 7091575
    Abstract: The invention includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality of parallel open conducting patterns embedded in a magnetic oxide or in an insulator and a magnetic material. Embedding the stacked open pattern inductor in a magnetic oxide or in an insulator and a magnetic material increases the inductance of the inductor and allows the magnetic flux to be confined to the area of the inductor. A layer of magnetic material may be located above the inductor and below the inductor to confine electronic noise generated in the stacked open pattern inductor to the area occupied by the inductor. The stacked open pattern inductor may be fabricated using conventional integrated circuit manufacturing processes, and the inductor may be used in connection with computer systems.
    Type: Grant
    Filed: October 25, 2002
    Date of Patent: August 15, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Method for fabricating transistors of different conduction types and having different packing densities in a semiconductor substrate
    Patent number: 7087492
    Abstract: A gate electrode layer is doped in a first section of a semiconductor substrate. By means of a patterning, encapsulated gate electrodes emerge from the gate electrode layer, which gate electrodes are arranged in a high packing density in a first section and are assigned to selection transistors of memory cells, and are arranged in a low packing density in a second section and are assigned to transistors of logic circuits. After a processing of the selection transistors, the encapsulated gate electrodes are uncovered in the second section and are subsequently doped in the same way in each case simultaneously with the respectively assigned source/drain regions. Together with a subsequent siliciding of the gate electrodes and of the source/drain regions, the performance of the transistors in the second section is significantly increased with little additional outlay.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: August 8, 2006
    Assignee: Infineon Technologies AG
    Inventors: Martin Popp, Lars Heineck
  • Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages
    Patent number: 7087995
    Abstract: A microelectronic package and method for forming such a package. In one embodiment, the package can include a microelectronic substrate having first connection sites, and a support member having second connection sites and third connection sites, with the third connection sites accessible for electrical coupling to other electrical structures. A plurality of electrically conductive couplers are connected between the first connection sites and the second connection sites, with neighboring conductive couplers being spaced apart to define at least one flow channel. The at least one flow channel is in fluid communication with a region external to the microelectronic substrate. The generally non-conductive material can be spaced apart from the support member to allow the microelectronic substrate to be separated from the support member.
    Type: Grant
    Filed: November 3, 2003
    Date of Patent: August 8, 2006
    Assignee: Micron Technology, Inc.
    Inventors: William Mark Hiatt, Warren Farnworth