Abstract: A second laser light of a continuous wave oscillation is irradiated to a region melted by a first laser light of a pulsed oscillation having a harmonic. Specifically, the first laser light has a wavelength not longer than that of visible light (830 nm, preferably not more than 780 nm). The absorption coefficient of the second laser light to a semiconductor film considerably increases because the semiconductor film is melted by the first laser light, and therefore the second laser light becomes easy to be absorbed in the semiconductor film.

Abstract: A memory cell having a bit line contact is provided. The memory cell may be a 6F2 memory cell. The bit line contact may have a contact hole bounded by insulating sidewalls, and the contact hole may be partially or completely filled with a doped polysilicon plug. The doped polysilicon plug may have an upper plug surface profile that is substantially free of concavities or substantially convex. Similarly, a storage node contact may comprise a doped polysilicon plug having an upper plug surface profile that is substantially free of concavities or that is substantially convex. Additionally, a semiconductor device having a conductive contact comprising a polysilicon plug may is provided. The plug may contact a capacitor structure.

Abstract: Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the active areas having a width of less than one micron, and with some of the active areas having different widths. A gate line is formed over the active areas to provide transistors having different threshold voltages. Preferably, the transistors are provided with different threshold voltages without using a separate channel implant for the transistors. In another embodiment, a plurality of shallow trench isolation regions are formed within a substrate and define a plurality of active areas having widths at least some of which being no greater than about one micron (or less), with some of the widths preferably being different.

Abstract: A method to form a very low resistivity interconnection in the manufacture of an integrated circuit device is achieved. A bottom conductive layer is formed overlying a substrate. The bottom conductive layer creates a first electrical coupling of a first location and a second location of the integrated circuit device. A dielectric layer is formed overlying the bottom conductive layer. A top conductive layer is formed overlying the dielectric layer. The top conductive layer is coupled to the bottom conductive layer through openings in the dielectric layer to form a second electrical coupling of the first location and the second location. A metal wire is bonded to the top conductive layer to form a third electrical coupling of the first location and the second location to complete the very low resistivity interconnection in the manufacture of the integrated circuit device.

Abstract: Processing a semiconductor wafer can include forming a plurality of Light Emitting Devices (LED) on a semiconductor wafer having a first thickness. The plurality of LEDs on the wafer are brought into contact with a surface of a carrier to couple the wafer to the carrier. The first thickness of the wafer is reduced to a second thickness that is less than the first thickness by processing the backside of the wafer. The carrier is separated from the plurality of LEDs on the wafer and the wafer is cut to separate the plurality of LEDs from one another. Related devices are also disclosed.

Abstract: Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the active areas having a width of less than one micron, and with some of the active areas having different widths. A gate line is formed over the active areas to provide transistors having different threshold voltages. Preferably, the transistors are provided with different threshold voltages without using a separate channel implant for the transistors. In another embodiment, a plurality of shallow trench isolation regions are formed within a substrate and define a plurality of active areas having widths at least some of which being no greater than about one micron (or less), with some of the widths preferably being different.

Abstract: A method of manufacturing a thin film transistor that provides high electric field mobility is disclosed.

Abstract: A method of forming micro-components is disclosed. The method includes pretesting and conditioning of the micro-components. The micro-components that fail testing or conditioning are discarded, and those remaining are assembled into a panel.

Abstract: A method for manufacturing a semiconductor device is provided including: providing a reinforcing member on one surface of a wiring substrate that has a first region where a semiconductor chip is mounted and a second region around the first region, and has terminals extending from the first region to the second region formed on another surface thereof, in a manner that the reinforcing member overlaps the terminals and a part thereof protrudes from the first region to the second region; punching through from a surface side having the reinforcing member in the wiring substrate, thereby continuously cutting the reinforcing member from an inboard side thereof to an outboard side along a boundary between the first region and the second region; and punching through from the surface side having the reinforcing member in the wiring substrate, thereby cutting the terminals along the boundary between the first region and the second region.

Abstract: Noble metal may be used as a non-oxidizing diffusion barrier to prevent diffusion from copper lines. A diffusion barrier may be formed of a noble metal formed over an adhesion promoting layer or by a noble metal cap over an oxidizable diffusion barrier. The copper lines may also be covered with a noble metal.

Abstract: The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, conductive metal silicide is formed on a transistor source/drain region and which is spaced from an anisotropically etched sidewall spacer proximate a gate of the transistor.

Abstract: A method for attaching a substrate such as a semiconductor wafer in which cracking or chipping can be prevented when the substrate is thinned involves applying adhesive liquid onto a circuit (element)-formed surface of a semiconductor wafer. The adhesive liquid undergoes preliminary drying, so that its flowability is reduced and it can keep its shape as an adhesive layer. For the preliminary drying, heating is conducted for 5 minutes at a temperature of 80° C. by using an oven. The thickness of the adhesive layer is determined based on the irregularities of the circuit which has been formed on the surface of the semiconductor wafer. Next, a supporting plate is attached to the semiconductor wafer on which the adhesive layer of a desired thickness has been formed.

Abstract: With a microwave FET, the internalized Schottky junction capacitance or pn junction capacitance is small and these junctions are weak against static electricity. However, with a microwave device, a protecting diode could not be connected since the increase of parasitic capacitance resulting from this method causes degradation of the high frequency characteristics. Therefore, to eliminate this problem, a semiconductor device is provided, wherein two paths, extending from a gate electrode pad to a gate electrode on an operating region, are arranged, with one path running near a source electrode pad, the other path running near a drain electrode pad, and at the respective parts where a path becomes close to a pad, the abovementioned protecting elements are connected between the gate electrode and source electrode and between the gate electrode and drain electrode to improve the electrostatic breakdown voltage of the FET from approximately 100V to 700V.

Abstract: Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the active areas having a width of less than one micron, and with some of the active areas having different widths. A gate line is formed over the active areas to provide transistors having different threshold voltages. In one embodiment, the transistors are provided with different threshold voltages without using a separate channel implant for the transistors.

Abstract: A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer. In another embodiment of the invention there is provided a semiconductor structure including a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing. In yet another embodiment of the invention there is provided a semiconductor structure including a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer.

Abstract: Provided are a metal-polishing liquid that comprises an oxidizing agent, an oxidized-metal etchant, a protective film-forming agent, a dissolution promoter for the protective film-forming agent, and water; a method for producing it; and a polishing method of using it. Also provided are materials for the metal-polishing liquid, which include an oxidized-metal etchant, a protective film-forming agent, and a dissolution promoter for the protective film-forming agent.

Abstract: A method of reducing the amount of halogenated materials in a halogen-containing environment. The method comprises introducing an aluminum compound into the halogen-containing environment, reacting the aluminum compound with the halogenated material to form a gaseous reaction product, and removing the gaseous reaction product from the environment. The aluminum compound may be a trialkylaluminum compound, an alane, an alkylaluminum hydride, an alkylaluminum halide, an alkylaluminum sesquihalide, or an aluminum sesquihalide. The aluminum compound may alternatively form a solid aluminum product, which is deposited on a surface associated with the halogen-containing environment or onto a semiconductor disposed therewithin. The halogenated material is incorporated into the solid aluminum product, forming an inert film within which the halogenated material is trapped.

Abstract: The present invention is to provide an electrical connection material through which an electrical connection via conductive particles can be performed reliably regardless of a little unevenness of an object. The electrical connection material is an electrical connection material 100 for electrically connecting an electrical connection portion of a first object 4 and an electrical connection portion of a second object 2. The electrical connection material 100 comprises a first film-like adhesive layer 6 which is a film-like adhesive layer arranged on the first object 4 and is composed of a plurality of conductive particles 7, a first binder 8 containing the conductive particles 7, and a first filler F1 and a second film-like adhesive layer 9 which is arranged on the first film-like adhesive layer 6 and is composed of a second binder 9A whose viscosity is lower than that of the first binder 8 and a second filler F2.

Abstract: Systems and methods are described for controlled alignment of catalyticaly grown nanostructures in a large-scale synthesis process. An apparatus includes an electrode including: a protruding section defining an edge; and a nonprotruding section coupled to the protruding section, where the edge is adapted to deflect an electric field generated with the electrode and at least one section selected from the group consisting of the protruding section and the nonprotruding section is adapted to support a substrate for the growth of elongated nanostructures.

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.