Patents Examined by Laura M Schillinger
  • Semiconductor device and its manufacture
    Patent number: 7157731
    Abstract: In a logic area, impurities are doped into the gate electrode and the source/drain diffusion regions of a MIS transistor. Thereafter in a memory cell area, word lines are patterned, source/drain regions are formed, and contact holes are formed. Side wall spacers of the MIS transistor in the logic area are made of silicon oxide. A semiconductor device of logic-memory can be manufactured by a reduced number of manufacture processes while the transistor characteristics are stabilized and the fine patterns in the memory cell are ensured.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: January 2, 2007
    Assignee: Fujitsu Limited
    Inventors: Toshio Taniguchi, Taiji Ema, Toru Anezaki
  • Non-volatile flash semiconductor memory and fabrication method
    Patent number: 7157768
    Abstract: In a semiconductor memory, a plurality of FinFET arrangements with trapping layers or floating gate electrodes as storage mediums are present on respective top sides of fins made from semiconductor material. The material of the gate electrodes is also present on two side walls of the fins, in order to form side wall transistors, and between the gate electrodes forms parts of a word line belonging to the corresponding fin.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: January 2, 2007
    Assignee: Infineon Technologies AG
    Inventors: Franz Hofmann, Erhard Landgraf, Wolfgang Rosner, Michael Specht, Martin Staedele
  • Method of fabricating polycrystalline silicon thin film for improving crystallization characteristics and method of fabricating liquid crystal display device using the same
    Patent number: 7153762
    Abstract: A crystallization method of an amorphous semiconductor layer includes providing an amorphous semiconductor layer having a first thickness, crystallizing the amorphous semiconductor layer in a first direction, partially reducing the crystallized semiconductor layer to a second thickness less than the first thickness and crystallizing the etched semiconductor layer in a second direction.
    Type: Grant
    Filed: September 15, 2003
    Date of Patent: December 26, 2006
    Assignee: LG.Philips LCD Co., Ltd.
    Inventor: Sang Hyun Kim
  • Seed layer processes for MOCVD of ferroelectric thin films on high-k gate oxides
    Patent number: 7153708
    Abstract: A method of forming a ferroelectric thin film on a high-k layer includes preparing a silicon substrate; forming a high-k layer on the substrate; depositing a seed layer of ferroelectric material at a relatively high temperature on the high-k layer; depositing a top layer of ferroelectric material on the seed layer at a relatively low temperature; and annealing the substrate, the high-k layer and the ferroelectric layers to form a ferroelectric thin film.
    Type: Grant
    Filed: October 12, 2005
    Date of Patent: December 26, 2006
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Tingkai Li, Sheng Teng Hsu
  • Process for oxide fabrication using oxidation steps below and above a threshold temperature
    Patent number: 7148153
    Abstract: A process for forming an oxide layer includes forming a first oxide portion over a substrate at a temperature below a threshold temperature. A second oxide portion is formed under the first oxide portion at a temperature above the threshold temperature. The substrate is illustratively oxidizable silicon and the threshold temperature is the viscoelastic temperature of silicon dioxide.
    Type: Grant
    Filed: December 11, 2002
    Date of Patent: December 12, 2006
    Assignee: Agere Systems Inc.
    Inventors: Yuanning Chen, Sundar Srinivasan Chetlur, Pradip Kumar Roy
  • Circuit suitable for vertical integration and method of producing same
    Patent number: 7144757
    Abstract: This invention relates to a vertically integratable circuit and a method for producing same. Unlike known methods for producing vertical electric connections, the present method uses process steps in the production of the vertically integratable circuit itself to permit vertical integration. This simplifies the sequence of production for vertically integratable circuits and thus the three-dimensional integrated circuit as a whole, thereby optimizing plant running times since process steps are saved. Because finished substrates are no longer the starting point for producing the vertical electric connections, an improved yield is moreover obtained since no process steps which could in particular change the already produced active circuit elements, such as steps with high process temperatures, are necessary any longer after production of the circuit elements.
    Type: Grant
    Filed: April 19, 2000
    Date of Patent: December 5, 2006
    Assignee: Giesecke & Devrient GmbH
    Inventor: Thomas Grassl
  • Method of producing crystalline semiconductor material and method of fabricating semiconductor device
    Patent number: 7144793
    Abstract: Disclosed are a method of producing a crystalline semiconductor material capable of improving the crystallinity and a method of fabricating a semiconductor device using the crystalline semiconductor material. An amorphous film is uniformly irradiated with a pulse laser beam (energy beam) emitted from an XeCl excimer laser by 150 times so as to heat the amorphous film at such a temperature as to partially melt crystal grains having the {100} orientations with respect to the vertical direction of a substrate and melt amorphous film or crystal grains having face orientations other than the {100} orientations. Silicon crystals having the {100} orientations newly occur between a silicon oxide film and liquid-phase silicon and are bonded to each other at random, to newly form crystal grains having the {100} orientations.
    Type: Grant
    Filed: August 21, 2003
    Date of Patent: December 5, 2006
    Assignee: Sony Corporation
    Inventors: Dharam Pal Gosain, Akio Machida, Kazushi Nakano, Toshio Fujino, Junichi Sato
  • Multi-layer dielectric containing diffusion barrier material
    Patent number: 7144825
    Abstract: A method for forming a dielectric is disclosed. The method comprises forming a first dielectric layer over semiconductor material. A diffusion barrier material is introduced into the first dielectric layer. Lastly, a second dielectric layer is formed over the first dielectric layer after the introducing.
    Type: Grant
    Filed: October 16, 2003
    Date of Patent: December 5, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Olubunmi O. Adetutu, Tien Ying Luo, Hsing H. Tseng
  • Fabrication method of semiconductor integrated circuit device
    Patent number: 7144755
    Abstract: At the time of performing resin molding for a matrix frame in the fabrication of semiconductor integrated circuit devices, a predetermined amount of air is fed into each of first cavities in a first row and second cavities in a second row, the first and second cavities being formed in a matrix arrangement in a lower mold of a molding die, so as to pressurize the interiors of the cavities, and a sealing resin is charged into the cavities, while the pressure therein is regulated in such a manner that the charging speeds of the sealing resin become equal in all of the cavities, whereby it is possible to stabilize the quality of the product being obtained.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: December 5, 2006
    Assignees: Renesas Technology Corp., Eastern Japan Semiconductor Technologies, Inc.
    Inventors: Bunshi Kuratomi, Fukumi Shimizu, Kenichi Imura, Katsushige Namiki, Fumio Murakami
  • Application of different isolation schemes for logic and embedded memory
    Patent number: 7141468
    Abstract: The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: November 28, 2006
  • Method to manufacture LDMOS transistors with improved threshold voltage control
    Patent number: 7141455
    Abstract: A double diffused region (65), (75), (85) is formed in an epitaxial layer (20). The double diffused region is formed by first implanting light implant specie such as boron through an opening in a photoresist layer prior to a hard bake process. Subsequent to a hard bake process heavy implant specie such as arsenic can be implanted into the epitaxial layer. During subsequent processing such as LOCOS formation the double diffused region is formed. A dielectric layer (120) is formed on the epitaxial layer (20) and gate structures (130), (135) are formed over the dielectric layer (120).
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: November 28, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Binghua Hu, Howard S. Lee, Henry L. Edwards, John Lin, Vladimir N. Bolkhovsky
  • Method and apparatus for performing whole wafer burn-in
    Patent number: 7138284
    Abstract: A method and apparatus for burning in a semiconductor wafer having a plurality of active devices utilizes temporary conductive interconnect layers to separately couple at least a portion of the anodes of the active devices together as well as at least a portion of the cathodes of the devices together. A simplified probed pad, having a reduced number of contacts may then be utilized to apply a substantially constant voltage or current to the devices. The temporary conductive interconnect layer may be patterned to include device level resistors or array level resistors that may be used to mitigate the effects of short circuits or open circuits on the processing of the devices.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: November 21, 2006
    Assignee: Optical Communication Products, Inc.
    Inventors: John Wasserbauer, Stewart A. Feld
  • Method of forming silicon carbide films
    Patent number: 7138332
    Abstract: To deposit silicon onto a substrate, there is introduced into a reaction zone a gas including source gases of silicon, carbon, nitrogen and an inert gas. An electric field is generated using low and high frequency RF power to produce a plasma discharge in the reaction zone to cause the deposition. The average power on the substrate is substantially constant. A ratio of low frequency RF power to total RF power is less than about 0.5.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: November 21, 2006
    Assignee: ASM Japan K.K.
    Inventor: Kamal Kishore Goundar
  • Enhanced on-chip decoupling capacitors and method of making same
    Patent number: 7138678
    Abstract: An apparatus including a capacitor formed between metallization layers on a circuit, the capacitor including a bottom electrode coupled to a metal layer and a top electrode coupled to a metal via wherein the capacitor has a corrugated sidewall profile. A method including forming an interlayer dielectric including alternating layers of dissimilar dielectric materials in a multilayer stack over a metal layer of a device structure; forming a via having a corrugated sidewall; and forming a decoupling capacitor stack in the via that conforms to the sidewall of the via.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: November 21, 2006
    Assignee: Intel Corporation
    Inventors: Bruce A. Block, Richard Scott List
  • Vertical MOSFET SRAM cell
    Patent number: 7138685
    Abstract: A method of forming an SRAM cell device includes the following steps. Form pass gate FET transistors and form a pair of vertical pull-down FET transistors with a first common body and a first common source in a silicon layer patterned into parallel islands formed on a planar insulator. Etch down through upper diffusions between cross-coupled inverter FET transistors to form pull-down isolation spaces bisecting the upper strata of pull-up and pull-down drain regions of the pair of vertical pull-down FET transistors, with the isolation spaces reaching down to the common body strata. Form a pair of vertical pull-up FET transistors with a second common body and a second common drain. Then, connect the FET transistors to form an SRAM cell.
    Type: Grant
    Filed: December 11, 2002
    Date of Patent: November 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Louis L. Hsu, Oleg Gluschenkov, Jack A. Mandelman, Carl J. Radens
  • Semiconductor device package and method of making the same
    Patent number: 7135765
    Abstract: A semiconductor device package and a method of making the same are provided. The semiconductor device includes a package substrate, a layer of conductive material, a group of channels, and a chip. The package substrate has a top layer. The top layer has a group of conductive vias formed therethrough. The conductive material layer is formed on the top layer of the package substrate. The group of channels are formed in the conductive material layer about at least some of the vias to define a group of contact pads on the vias. The chip is electrically coupled to the package substrate through the contact pads.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: November 14, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Muthiah Venkateswaran
  • Method of fabricating a semiconductor device comprising a gate dielectric made of high dielectric permittivity material
    Patent number: 7129563
    Abstract: A process and a device for fabricating a semiconductor device having a gate dielectric made of high-k material, includes a step of depositing, directly on the gate dielectric, a first layer of Si1?xGex, where 0.5<x?1, at a temperature substantially below the temperature at which a poly-Si is deposited by thermal chemical vapor deposition (CVD).
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: October 31, 2006
    Assignee: STMicroelectronics SA
    Inventors: Vincent Cosnier, Yves Morand, Olivier Kermarrec, Daniel Bensahel, Yves Campidelli
  • Semiconductor device and method manufacturing the same
    Patent number: 7122900
    Abstract: A semiconductor device according to this invention comprises a substrate 100 in which semiconductor elements are formed, a first conductor 301 at least a portion of the peripheral surface of which is made of a material comprising copper as a main ingredient, and a first insulative diffusion barrier layer 203 covering at least a portion of the first conductor 301. The first insulative diffusion barrier layer 203 is formed by using a gas mixture at least containing an alkoxy silane represented by the general formula (RO)nSiH4?n (n is an integer in a range from 1 to 3, R represents an alkyl group, an aryl group or a derivative thereof), and an oxidative gas by a plasma CVD. Thus, a semiconductor device comprising copper wiring of high reliability and with less wiring delay time can be provided.
    Type: Grant
    Filed: May 28, 2001
    Date of Patent: October 17, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Kenichi Takeda, Daisuke Ryuzaki, Kenji Hinode, Toshiyuki Mine
  • Angular substrates
    Patent number: 7122280
    Abstract: A square substrate has a pair of opposed major surfaces and peripheral end faces therebetween, wherein a tapered edge portion is disposed between the peripheral end face and each major surface to define an inner boundary with the major surface, and has a width of 0.2–1 mm from the peripheral end face. Both or either one of the major surfaces of the substrate has a flatness of up to 0.5 ?m in an outside region of the substrate that extends between a position spaced 3 mm inward from the peripheral end face and the inner boundary of the tapered edge portion.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: October 17, 2006
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Jiro Moriya, Masataka Watanabe, Satoshi Okazaki
  • Semiconductor integrated circuit and method of fabricating same
    Patent number: 7122833
    Abstract: A semiconductor integrated circuit comprising thin-film transistors in each of which the second wiring is prevented from breaking at steps. A silicon nitride film is formed on gate electrodes and on gate wiring extending from the gate electrodes. Substantially triangular regions are formed out of an insulator over side surfaces of the gate electrodes and of the gate wiring. The presence of these substantially triangular side walls make milder the steps at which the second wiring goes over the gate wiring. This suppresses breakage of the second wiring.
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: October 17, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Yasuhiko Takemura