Abstract: A method is presented for conveying information over a wireless interface in the form of a digitally encoded message. A set of bits is provided as a first piece of information to be transmitted, and a certain baseband signal processing method is applied to process the bits to be transmitted. In addition, a second piece of information is provided to be transmitted and the baseband signal processing method is selected from a set of allowed baseband signal processing methods in accordance with the provided second piece of information.

Abstract: An apparatus and method for providing control signals, comprising a processor coupled to a memory, for generating a signal sequence. The processor encodes the signal sequence into a plurality of symbols using a 5 pulse position modulated (5 PPM) scheme. Advantageously, the last position of each symbol encoded under the 5 PPM scheme is set to a low bit. The symbol sequence represents a signaling protocol having a payload portion and a header portion, wherein the header portion comprises a plurality of fields for defining the payload portion. The payload portion indicates keyboard characters or coordinates for a pointing device.

Abstract: Described is a transmission system for transmitting a multicarrier signal from a transmitter (10) to a receiver (20). The multicarrier signal comprises a plurality of subcarriers. The receiver (20) comprises a channel estimator (28) for estimating amplitudes of the subcarriers and for estimating time derivatives of the amplitudes. The receiver (20) further comprises an equalizer (24) for canceling intercarrier interference included in the received multicarrier signal in dependence on the estimated amplitudes and derivates (29). The receiver (20) comprises a multiplication by a N×N leakage matrix, and wherein the multiplication is implemented as a sequence of an N-point IFFT (82), N pointwise multiplications (84) and an N-point FFT (86). multiplications (84) and an N-point FFT (86).

Abstract: An improved receiver architecture is disclosed comprising a latching mechanism coupled to receive a data stream, and a signal generator for generating latching control signals for controlling the operation of the latching mechanism. The signal generator generates one latching control signal per data period of the data stream, with each latching control signal coinciding approximately with the midpoint of a corresponding data period. The signal generator generates the latching control signals based upon a reference signal, which in one embodiment, coincides approximately with the midpoint of a data period of the data stream. The receiver may further comprise an adjustable delay element and a delay adjustment control. The adjustable delay element receives a clock signal and imposes a variable delay thereon to derive the reference signal used to generate the latching control signals. The magnitude of the variable delay is controlled by the delay adjustment control.

Abstract: A method for coherent phase synchronous CDMA communications between a gateway and multiple subscribers via multiple transponder platforms that includes the step of synchronizing a local reference clock for each subscriber in a service area to a single master reference clock for multiple transponder platforms wherein the distance separating the transponder platforms is constrained to a range wherein the local reference clocks for all subscribers have substantially the same phase with respect to the master reference clock.

Abstract: Variable Aperture Coded (VAC) signals for VAC modulation are advantageously generated by a digital signal processor (12) that yields a VAC signal having a single narrow peak in the positive frequency region. A Discrete-Time Hilbert transformer (12) isolates only the positive spectral peaks, thus yielding a VAC signal that affords greater control over zero crossings.

Abstract: A clock switching technique allows selecting an input clock signal from two clock sources. The two clock sources are asynchronous to one another and a clock select signal is used to determine which of the clocks will be switched onto the clock output line. The clock select signal is asynchronous to both clock sources and can be either from a programmable bit implemented under software control or as a single signal generated from some other logic block. The technique guarantees that the switching to the desired clock based on the binary value of the clock select signal onto the clock line is glitch-free. The clock switching technique is independent of the two clock source frequencies as well as the system clock frequency.

Abstract: A specific cyclic sequence of frequencies for use as a carrier hop sequence by a mobile station in a mobile radio communication system is chosen from a list of usable frequencies by means of a sequence of indices derived from the unique identifier of the mobile station. The indices are used to indicate respective positions in the list and hence to choose a succession of frequencies to make up one cycle of the cyclic sequence. The list is updated between successive choices of a frequency therefrom, making it possible to ensure, by appropriate exclusions from the list each time, that the succession of frequencies chosen satisfies predetermined constraints such as minimum hop distance and minimum stay-away time, either absolutely or to the maximum extent possible.

Abstract: A wireless network transmits digital data. The network includes an active transceiver to transmit carrier waves at a succession of preselected frequencies and a transponder. The transponder transmits digital data to the active transceiver by partially reflecting the carrier waves.

Abstract: A multi-client ADSL modem network (10) that can be configured for a home or office network when multiple ADSL client modems (18) are installed in different communication terminals (22). One ADSL modem (14) at a central office (12) coordinates the remote multi-client modems (18) for communication over a single twisted pair loop carrier phone line (16), allowing the connected modems (18) to communicate not only with the CO modem (14), but also with each other by sharing frames, tones, or by code division techniques on upstream channels. The CO modem (14) operates as a network hub and/or arbitrator, and facilitates one ADSL modem to become the master modem and maintain a superframe. The present invention provides home network ADSL service without extra wiring or equipment, thus providing a low cost approach for home networking of ADSL service.

Abstract: A method and arrangements are provided for transmitting frames of digital information over a wireless communication connection between a transmitter and a receiver. In the transmitter, a certain sequence of bits within each frame of digital information is convolutionally encoded and punctured before transmitting the frame over a wireless communication connection. The receiver decodes and depunctures the sequence of bits within each frame of digital information, that was convolutionally encoded and punctured, after receiving the frame over a wireless communication connection. The transmitter rearranges the sequence of bits within each frame of digital information that is to be convolutionally encoded and punctured, before convolutionally encoding and puncturing it.

Abstract: In a spread spectrum transmitter, a number of spread spectrum channel signals are multiplexed into a digital amplitude signal by a multiplexer, and the time-average power of the digital amplitude signal is determined by an average calculator. The digital amplitude signal is interpolated by an interpolator, scaled according to a first scale factor by a bit shifter and converted to an analog amplitude signal by a D/A converter. The analog amplitude signal is then scaled according to a second scale factor in a gain controlled amplifier. The first and second scale factors are complementarily varied by a control circuit according to the output of the average calculator so that the carrier-to-noise ratio of the transmitter is maintained substantially constant regardless of the varying power level of the multiplexed signals.

Abstract: In a radio communication method whereby adaptive modulation is performed, a method is used whereby pilot symbol signal points are arranged in the in-phase-quadrature plane (IQ plane) so that the reception sensitivity of a receiving apparatus is made optimal in the respective modulation methods while maintaining the average transmission output power of the transmitting apparatus at a fixed level. By this means, it is possible to arrange pilot symbol signal points and improve the reception sensitivity characteristics of a receiving apparatus while maintaining the average transmission output power of the transmitting apparatus at a fixed level.

Abstract: The invention relates to a method of processing multipath-propagated components of a signal in a communications system. In the method, a signal transmitted on the radio channel of the communications system is received in a RAKE receiver and an impulse response of the radio channel is formed. In the method, one or more taps having the highest signal energy in the impulse response are located and matched to a short matched filter. A weighting value for the impulse response is calculated on the basis of the one or more taps in the matched filter and a deviation between the weighting value and the center point of the matched filter is compared with a threshold value set for the deviation. The matched filter is moved toward the deviation when the deviation exceeds the threshold value set for the deviation.

Abstract: The invention relates to a synchronous, clocked communication system, for example a distributed automation system, the stations of which can be arbitrary automation components which are coupled to one another via a data network (1) for the purpose of mutual data exchange. In this arrangement, all possible bus systems such as, e.g. field bus, professional field bus, Ethernet, industrial Ethernet etc. are available for use as the data network (1) of the communication system. One station of this communication system is designated as timing generator and ensures the distribution and maintenance of the communication clock used to and by all stations. The timing generator can also introduce a relative clock (9) in the entire communication system at all stations via the same mechanism. This station is thus also the master of the relative clock (9) or the applicable relative time (16).

Abstract: Method for forming and/or determining a synchronization sequence, a synchronization method, a transmitting unit and a receiving unit, the formation of synchronization sequences, which are based on partial signal sequences, includes a second partial signal sequence being repeated and modulated in the process by a first partial signal sequence.

Abstract: A method and apparatus for decoding turbo codes using a sliding window method is disclosed. In decoding a received sequence using a Maximum A Posteriori (MAP) algorithm, a learning by a backward processing is performed for a predetermined length and first resultant values of an L-symbol length sequence and second resultant values of a W-symbol length sequence calculated by a backward processing are stored. Third resultant values are calculated by a forward processing. The calculation of the third resultant values overlaps in time with the next learning. A decoding symbol output is determined using the third resultant values and the second resultant values of the previous window.

Abstract: A source signal transmitted through multiple channels having space, time and frequency diversities to generate multiple received signals is recovered by an iterative associative memory model with dynamic maximum likelihood estimation. A current symbol vector representing the multiple received signals is projected to a net-vector using a linear matrix operation with a weight matrix W. The weight matrix is obtained by a singular value decomposition of an input symbol sequence. The net-vector is mapped to a nearest symbol vector using a non-linear operation with an activation function. The projecting and mapping steps are repeated until the nearest symbol vector converges to a valid symbol vector representing the source signal.

Abstract: The invention provides a decoding circuit and a decoding method of a Viterbi decoder. The decoding circuit of the Viterbi decoder includes a branch metric unit, an add-compare-select unit and a path memory unit. The path memory unit includes a data string controller, a trace write-in register array, an idling register array and a decoding register array. In this invention, a run length limited code is used for effectively solving the problem of generating a complicated trellis diagram after the trellis diagram of the Viterbi decoder is subjected to a longitudinal arrangement. In addition, the register array can perform other operations at different times. Accordingly, a high decoding speed of the Viterbi decoder can be achieved without requiring a lot of registers for data processing.

Abstract: For encoding a source sequence of symbols (u) as an encoded sequence, the source sequence (u) is divided into p1 first sub-sequences (Ui), p1 being a positive integer, and each of the first sub-sequences (Ui) is encoded in a first circular convolutional encoding method. The source sequence (u) is interleaved into an interleaved sequence (u*), and the interleaved sequence (u*) is divided into p2 second sub-sequences (U?i), p2 being a positive integer. Each of the second sub-sequences (U?i) is encoded in a second circular convolutional encoding method. At least one of the integers p1 and p2 is strictly greater than 1 and at least one of the first sub-sequences (Ui) is not interleaved into any of the second sub-sequences (U?j). (It is noted that the above underlining of the following symbols is original, and is meant to be permanent: u, Ui, u*, U?i, U?j).