Abstract: A code multiplexer multiplexes spread data output from a spreader to generate code-multiplexed data. A reference data generator generates redundant data with constant power and with no information contained therein. A data adder adds the redundant data to the code-multiplexed data. A variable amplifier variably amplifies the transmit power of the code-multiplexed data and the redundant data to obtain transmit output data. A difference value calculator calculates a difference value between a target amplitude value and the amplitude of the amplified redundant data. A gain controller generates, based on the difference value, a gain control signal to control the gain of the variable amplifier. It is thereby possible to perform gain compensation with a small calculation amount and with high accuracy.

Abstract: An apparatus comprising an analog circuit and a digital circuit. The analog circuit may be configured to generate a plurality of samples of an input signal in response to a plurality of phases of a reference clock. The digital circuit may be configured to (i) measure a width of a symbol in the input signal in response to the plurality of samples and the plurality of phases of the reference clock and (ii) adjust the measured width in response to a correction signal.

Abstract: A Direct Sequence Spread Spectrum (DSSS) receiver system (100) combines and orders the soft symbols from associated information channels. The system permits a QPSK channel to be demodulated as a pair of BPSK channels, and the soft symbols of the demodulated BPSK channels to be multiplexed into a single information channel. The receiver system (100) includes a plurality of demodulating fingers (102–106). Each demodulating finger accepts modulation parameters and a sample stream, while supplying soft symbols with indexing information so that information channels can be subsequently multiplexed into a single information channel. A method for ordering the soft symbols of associated information channels in a DSSS system is also provided.

Abstract: A method of frame synchronization for serial data transmission is presented herein. A transmitting circuit in a data communication apparatus converts frame data into serial data and transmits the same, and following the serial data, the transmitting circuit transmits frame synchronization data varying several times in the interval from an edge of a clock signal to an edge of the next clock signal; a receiving circuit receives the frame data and detects two or more variations in the same interval to find the end of the frame data, by receiving the serial data from a signal line, serial data is transmitted while carrying out frame synchronization.

Abstract: Systems and methods are disclosed for improving DSL performance, including ADSL and VDSL performance, over a local loop between a telephone company central office and a customer premises. In particular, a loop extender is coupled to the local loop and differentially amplifies downstream and upstream DSL signals to at least partially compensate for DSL signal attenuation that occurs as DSL signals pass over the local loop. Pursuant to one embodiment, the loop extender includes an upstream filter/amplifying equalizer, a downstream filter/amplifying equalizer, a differential amplifier pair, an inverting amplifier, and a pair of electromagnetic hybrids, which couple the loop extender to the loop and provide upstream and downstream signal amplification. In another embodiment, the loop extender includes POTS loading coils to improve the POTS or voice band transmission over the local loop. According to this embodiment, the loop extender provides both improved POTS band signal transmission and DSL service.

Abstract: An apparatus comprising an analog circuit, a first digital circuit, and a second digital circuit. The analog circuit may be configured to generate a plurality of samples of an input signal in response to a plurality of phases of a reference clock. The first digital circuit may be configured to generate (i) one or more data signals, (ii) a first strobe signal, and (iii) a second strobe signal in response to the plurality of samples, the plurality of phases, and a correction signal. The second digital circuit may be configured to generate the correction signal and a width signal in response to (i) the one or more data signals, (ii) the first strobe signal, and (iii) the second strobe signal.

Abstract: A method for communicating serial input data over a transmission link. Serial input data is partitioned into parallel data elements and is coded prior to rotation by an invertible linear mapping. Resulting frames of parallel sign elements are transmitted over the link. After receipt from the link, the signal is assembled into frames of parallel signal elements which are de-rotated by an inverse linear mapping, then decoded. Thresholding the result of the inverse mapping recovers the parallel data elements, which are then re-assembled into serial output data. The linear mapping employs: 1) commuting rotation matrices for convolutionally rotating data vectors into signal vectors and vice-versa; 2) filter bank polyphase rotation matrices; or 3) computationally efficient multi-rate wavelet filter banks. Coefficients of the rotation matrix of the receiver are adaptively equalized to correct for transmission path distortion.

Abstract: A digital data storage (DDS) system for reading DDS tapes employs a partial response maximum likelihood detection system which utilises redundancy in the 8-10 DC free modulation encoding to reduce low frequency noise. The system incorporates a time-varying trellis decoder which embodies some of the PR1 rules together with the rules regarding the charge state or the digital sum variation (DSV) implicit in 8-10 modulation coding. The decoder operates to reject low frequency noise such as that caused by crosstalk noise between adjacent tracks on the tape. The trellis topography has been considerably simplified by adopting a two step six state trellis which operates on bit pairs and in which the states relate to the current DSV value, and sign of the previous bit.

Abstract: A method of frame synchronization serial data transmission. A transmitting circuit in a data communication apparatus converts frame data into serial data and transmit the same, and following the serial data, the transmitting circuit transmits frame synchronization data varying several times in the interval from an edge of a clock signal to an edge of the next clock signal; a receiving circuit receives the frame data and detects twice or more variations in the same interval to find out the end of the frame data, by receiving the serial data from a signal lines, serial data is transmitted while carrying out frame synchronization.

Abstract: A wireless radiofrequency data communication system has a base-station with N first groups and a signal processing-unit with a memory and processor. Each first group has a receiver-unit provided with a receiver and at least one antenna which is connected to the receiver-unit, and the signal processing-unit is connected with each of the first groups for processing receive-signals generated by each of the first groups. The base station further has M second groups for transmitting radiofrequency signals to the first groups. Each second group has a transmitter-unit provided with a transmitter and at least one antenna which is connected to the transmitter-unit. The memory of the signal processing-unit is provided with information about the transfer-functions of radiofrequency signals from each of the antennas of the second groups to each of the antennas of the first groups, and the transmitters and receivers operate on essentially the same radio frequency or radiofrequency-band.

Abstract: A symbol synchronizer comprises a distance metric computation module for computing a metric from received samples using a distance metric function within a symbol sampling period and based on a timing signal for each of the possible symbols in a constellation, a control signal computation module for selecting a smallest and a second smallest metrics, producing a difference by subtracting the smallest metric from the second smallest metric, and deriving a control signal from the difference, and a voltage-control clock for producing the timing signal based on the control signal.

Abstract: A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displaced clock signals. A Low Voltage Differential Signaling buffer connected to the phase controlled read circuit transmits the data signals in a Low Voltage Differential Signaling mode. The phase displaced clock signals operate in lieu of a higher clock rate in order to reduce power consumption.

Abstract: The device can be used for generating, in the framework of a CDMA communications terminal, both Walsh-Hadamard channeling codes and OVSF channeling codes. The device comprises a code generator preferably configured for generating Walsh-Hadamard codes. When the device is used for generating Walsh-Hadamard codes, the corresponding index values, applied to an input of the device, are sent to the input of the code generator. Generation of OVSF codes envisages, instead, that the corresponding indices, sent to an input of the device, undergo mapping, which enables generation, starting from the OVSF code, of the corresponding index identifying a string of symbols that is identical within the Walsh-Hadamard code. In this way each string of OVSF code symbols is generated, so producing, by means of the code generator, the generation of the identical string of symbols included in the Walsh-Hadamard code.

Abstract: A method of estimating a DC offset value of a signal includes estimating a DC offset value of a preamble part of the signal using a pair of diodes (D1, D2) and a resistor (R) connected in parallel. During receipt of the data part of the signal, the diode pair (D1, D2) is switched out of the circuit by a switch (SW). During reception of the data part, the DC level is estimated using a low pass filter (R,C).

Abstract: A method of transmitting data signals from at least two transmitting terminals to at least one receiving terminal with a spatial diversity antenna comprises transmitting from the transmitting terminals transformed data signals, being transformed versions of the data signals; receiving on the spatial diversity means received data signals being at least function of at least two of the transformed data signals; subband processing of at least two of the received data signals in the receiving terminal; and determining estimates of the data signals from subband processed received data signals in the receiving terminal.

Abstract: A bistable memory device changes logic state each time an event occurs. The bistable memory device has an logic output coupled to a digital processor input. The digital processor reads the logic state of the bistable memory device from its logic output and compares the logic state read to a stored previous logic state obtained from a previous read. If the logic state read and the stored previous logic state are the same, then no event has occurred during the time between the read and previous read of the logic states of the bistable memory device. If different, then an event has occurred during the time between the read and previous read of the logic states of the bistable memory device. The event detection may be used in combination with a digital system communicating by serial digital data transmissions.

Abstract: A method and an apparatus are provided in this invention to select an optimal swapping technique in discrete multi-tone system. The algorithm for performing gain-swapping is also proposed in the present invention. A swapping technique is selected from gain-swapping and a combination of bit-swapping and gain-swapping based on two index values such that the difference between the maximum mean square error (MSEmax) and the minimum mean square error (MSEmin) is minimized and the gain factor constraints are met. The first index value I is representative of range of improvement when adopting the gain-swapping as the swapping technique, and the second index value J is representative of range of improvement when adopting a combination of the gain-swapping and the bit-swapping as the swapping technique.

Abstract: A device for detecting a demodulated signal received by a spread spectrum receiver and converted into digital samples. The device is characterized by a matched filter for calculating the correlation between an incoming signal and at least one reference signal, an oscillator for generating a sampling frequency, and a sampling circuit for re-sampling the demodulated digital sample signal at the sampling frequency, which is such that the timing of samples of the references signals of the matched filter corresponds to the timing of a sample signal going from the sampling circuit to the matched filter. The device also includes a multiplier in which the sample signal is multiplied by a carrier replica generated locally before the sampling circuit or thereafter, to remove the carrier from the sample signal.

Abstract: A mobile station adapted to be used in a radio communications system includes a receiver apparatus adapted to receive blocks of distorted information bits at a first rate from a transmitter via a communications link, and a first detecting apparatus adapted to detect information bits from the distorted information bits. The mobile station also includes a second detecting apparatus adapted, when the quality of the received blocks of information bits is above a given level, to detect information bits from the distorted information bits using fewer computation resources than the first detecting apparatus.

Abstract: A method and device used in wireless mobile communication for multi-selection signal detection. In order to minimize the influence of frequency shift and phase rotation that reduces signal detection performance, the total number of samples used for the signal detection may be divided into an equal number of segments, on which the coherent accumulating sum is calculated. Various possible combinations will be made according to each coherent result. The combinations may then be coherent accumulated again. Finally, the optimum results may be selected as the detection results. To accomplish this result, the input signal is input to the matched filter unit, whose output will be sent to each branch unit. The phase adjustment and the coherent accumulation of the signal will be performed in each respective branch unit, and then sent to the branch selection unit where the branch output with the largest mode is selected as the output.