Abstract: The present invention is directed to an interference canceller for a DS-CDMA communication system and a radio communication device that performs multi-rate transmission and eliminates interference of high-rate channels by a simplified structure. In a DS-CDMA communication system that performs a multi-rate transmission including at least low-rate channels and high-rate channels, there is provided an interference canceller that includes an array antenna interference replicating unit. The interference replicating unit is used in high-rate channels that receive signals received via array antenna elements and creates interference replicas of the high-rate channels. The system also includes an adder 6, which subtracts the interference replicas from the received signal via the array antenna elements. Further a resultant interference-eliminated signal is applied to receivers for the low-rate and high-rate channels.

Abstract: A resolved component of a multi-path signal is assigned to a rake finger of a spread spectrum rake receiver. The resolved component is variably delayed. On the variably delayed resolved component, an early-late detection is performed so as to determine whether the resolved component arrived early or late with respect to an optimum arrival time. A first pulse is generated if the early-late detection determines that said resolved component arrived early. A second pulse is generated if the early-late detection determines that the resolved component arrived late. The first and second pulses are counted. The first pulse causes counting in a first direction and the second pulse causes counting in a second direction. From the counting, a fractional-chip delay timing adjustment signal is derived, and fed back to adjust the variably delaying of the resolved component. Also from the counting a chip delay phase adjustment signal is derived, and fed back to control a phase of a pseudo-noise generator.

Abstract: A demodulator determines a time of arrival of an access signal. Access signals that do not result in a time of arrival are discarded. Upon obtaining a time of arrival, the access signal is equalized and a training sequence of bits in the equalized access signal is compared to a reference sequence of bits. A burst confidence metric is obtained in the comparison by summing the number of matching bits. The access signal is discarded if the burst confidence metric is less than a threshold number. A decoder performs a parity check on access signals that have a burst confidence metric exceeding the threshold number. The access signal is discarded if the parity check fails. Upon passing the parity check, the access signal is re-encoded and compared to its received version. If a number of errors from the comparison exceeds a bit error threshold, the access signal is discarded.

Abstract: Methods and apparatus are presented herein for determining log likelihood ratios (LLRs) for code symbols. Pilot and code symbols are transmitted over diversity channels, which can be modeled as a slowly time varying system. A formulation for a multipath gain vector is derived herein based on the slowly time varying model. The multipath gain vector is then solved using iterative procedures. Using the solved multipath gain vector, the LLRs for code symbols are computed.

Abstract: A demodulation circuit for demodulating a multilevel digital modulation signal. Only an in-phase or quadrature component of the training signal generated in the demodulation circuit is used for equalization convergence. Tap coefficients of an equalizing training equalizer are updated by supplying either the in-phase or quadrature component so that the calculation amount can be reduced. When the equalization convergence is established, the obtained tap coefficients are rotated in phase and set to a data reproduction equalizer.

Abstract: Time tracking units with decision statistics mitigating or correcting for influences from nearby interfering paths. Interference mitigation is accomplished by appropriately selecting the parameters of the time tracking unit so that the contribution of the interference on the decision statistics of the time tracking unit is minimized. Interference cancellation is accomplished by evaluating and subtracting of the effect from the interfering paths on the decision statistics of the time tracking unit. Both urban and indoor communications may incorporate the interference avoidance or interference correction either in each time tracking unit of a rake-type receiver by inter-unit communication of timing adjustments and path energies or by software within a common processor.

Abstract: A receiving system or a received radio-wave estimation method is provided that can maintain received field strengths at a nearly uniform level under multipath conditions. The antenna switch can select outputs of four antennas at high speed. The high-frequency amplifier amplifies the output of the antenna switch and the demodulator demodulates amplified signals. The matched filter bank, surrounded with chain lines, receives a demodulated signal, for example, the I-phase component. In the matched filter bank, the phase shifter shifts respective signals output from four delay elements. The adder synthesizes the phase-shifted signals and then supplies the maximum matched output to the maximum level selector.

Abstract: A transmission diversity detection system that detects the presence or absence of a STTD (Space-Time Transmit Diversity) transmission diversity by a simple arithmetic operation. The transmission diversity detection circuit notifies presence or absence of a transmission diversity of spread spectrum communication by modulation of a synchronization channel (SCH).

Abstract: This invention provides a method for initializing the filter coefficients of a hybrid frequency-time domain adaptive equalizer device implementing frequency domain (FD) filter equalization in a forward path and a time domain (TD) filter equalization in a feedback path, with each filter unit having a plurality of adaptable filter taps. Preferably, in initializing the equalizer, the relation 1 + F G = H is obeyed “where (G) is the forward FD equalizer taps, (F) is” the Fast Fourier Transform of the feedback TD equalizer taps, and (H) is the estimated (frequency domain) response of the communications channel.

Abstract: A clock recovery method in digital signal sampling wherein the clock is generated from a phase-locking loop or PLL which multiples a given frequency by a whole number. The method includes comparing the relative position of the signals with respect to the clock so as to determine whether a selected type of the clock transitions is in phase with the same type of signal transitions by: producing over a clock period several zones, one zone corresponding to the selected type of transitions; analysing the signal transitions relatively to the clock uplink or downlink transitions; cumulating in the corresponding zone the analysis results; determining on the basis of the accumulation whether the sampling clock frequency and/or phase needs to be modified or not. The invention is applicable to signals derived from graphics cards.

Abstract: A clock generation apparatus generates a synchronous clock based on an input analog signal. The average of maximum and minimum values of a digital signal in a predetermined period is used as a threshold. Rise and fall times which are times when the threshold and an approximated line of two values of the digital signal crosses are detected. The time intervals between the adjacent rise and fall times are obtained during a predetermined period. The minimum value of the time intervals is used as the input rate. The synchronous clock is output on the basis of the input rate and the rise and fall times. The synchronous clock and a comparison signal which is obtained by comparing the threshold and the digital signal are supplied to a latch circuit, thereby outputting a synchronous signal.

Abstract: The invention relates to a method and a device for processing signals of a digital transmission system in general, and for estimating the frequency offset of the transmission system in particular. In one embodiment, the method according to the invention estimates the pulse response of the transmission system and shortens the pulse response by means of a variable prefilter. The duration of the shortened pulse response is, in particular, shorter than the duration of a known symbol sequence which is transmitted twice identically within one method cycle. By comparing samples of the received signal which correspond to the known identical symbols, the frequency offset is estimated reliably, and suitable measures can be taken to compensate it. Consequently, the efficiency of the receiver is substantially improved with respect to the recovery of the transmitted data.

Abstract: A redundant clock system and communications cards for utilizing the system, the system including a clock source for providing a reference signal for communication cards; an alternate clock source, coupled to the clock source, for providing an alternate reference signal for the communication cards; each of the communication cards including a clock generator, referenced to one of the reference signals for providing clock signals at frequencies corresponding to functions provided by each of the communications cards, and each of the communication cards arranged to couple to a surviving one of the reference signals when a failure of the other is detected.

Abstract: A distortion compensating apparatus for compensating for a distortion of a transmission power amplifier. A delay time decision unit calculates the correlation between a transmission signal and a feedback signal fed back from the output side of the transmission power amplifier while varying phase difference between both signals, and decides the total delay time caused in the transmission power amplifier and a feedback loop on the basis of the phase difference in which the correlation is the maximum. A delay unit delays the transmission signal before a distortion compensation processing by the total delay time, and inputs the delayed signal into a distortion compensating apparatus arithmetic unit, which calculates and stores a distortion compensation coefficient on the basis of the transmission signal and the feedback signal fed back from the output side of the transmission power amplifier.

Abstract: A limiting method is provided which limits signals having two components I channel and Q channel on two orthogonal coordinate axes within a predetermined range on the coordinate plane specified by the two coordinate axes, wherein the predetermined range is defined by concentric circles having the origin of the two coordinate axes as a center.