Abstract: A semiconductor structure that includes a resistor that is located within an interconnect dielectric material layer of an interconnect level is provided. The resistor includes a diffusion barrier material that is present at a bottom of a feature that is located in the interconnect dielectric material layer. In some embodiments, the resistor has a topmost surface that is located entirely beneath a topmost surface of the interconnect dielectric material layer. In such an embodiment, the resistor is provided by removing sidewall portions of a diffusion barrier liner that surrounds a metal-containing structure. The removal of the sidewall portions of the diffusion barrier liner reduces the parasitic noise that is contributed to the sidewall portions of a resistor that includes such a diffusion barrier liner. Improved precision can also be obtained since sidewall portions may have a high thickness variation which may adversely affect the resistor's precision.

Abstract: A method for manufacturing an organic electronic element capable of reducing unevenness in film thickness of a coating film is disclosed. A method for manufacturing an organic electronic element according to an embodiment of the invention is a method for manufacturing an organic electronic element including a functional layer containing an organic material, including a coating step of forming a functional layer by horizontally conveying a base material (110) having flexibility using a roll-to-roll process and coating a coating solution containing an organic material onto the base material (110) using a slit coat applicator (30) disposed above the base material (110), wherein in the coating step, the base material (110) is floated by air using an air floating stage (20) disposed below the base material (110) and the coating solution is coated onto the base material (110).

Abstract: The disclosure discloses a display substrate and a manufacturing method thereof, and a display device, the display substrate comprises a display region and a periphery region, a first electrode line is arranged at the periphery region, an insulating layer is arranged on the first electrode line, a first through hole is provided in the insulating layer at a position corresponding to the first electrode line, a contact electrode is provided in the first through hole, a second electrode line is arranged on the insulating layer, the second electrode line is electrically connected to the first electrode line through the contact electrode. In the disclosure, the contact electrode is provided between the first and second electrode lines, thus when the second electrode line is etched, the first electrode line is protected by the contact electrode from being damaged by etchant, thus saving production cost and improving production efficiency.

Abstract: Provided an LED display apparatus including: an LED substrate in which a plurality of LED elements emitting first-wavelength light are arranged in rows and columns; a first wavelength conversion sheet provided on the LED substrate and converting the first-wavelength light into second-wavelength light; and a second wavelength conversion sheet provided on the first wavelength conversion sheet and converting the first-wavelength light or the second-wavelength light into third-wavelength light.

Abstract: A method of dicing a bowed or warped semiconductor wafer includes cutting along the saw streets in a first direction on a first half of the wafer, where the first direction is parallel to the bowing, cutting along the saw streets in the first direction on a second half of the wafer opposite to the first half, and step-cutting along the saw streets in the second direction, such that all of the dies are separated from each other, and the sides of the die in the bowing direction are flat and the sides of the die perpendicular to the bowing direction are stepped.

Abstract: An optoelectronic semiconductor component having a light source, which emits primary radiation, a housing, and electrical terminals, wherein a conversion element, which is based on a matrix and at least two phosphors, is connected upstream of the optoelectronic semiconductor component. The matrix contains metal phosphate and preferably consists of metal phosphate. The phosphors partially or completely convert primary radiation. At least one first phosphor powder is embedded and fixed in a first inorganic matrix based on a metal phosphate, and at least one second phosphor powder is embedded and fixed in a second matrix based on a metal phosphate.

Abstract: A transparent light emitting diode film is disclosed. The transparent light emitting diode film includes a base, an electrode layer positioned on the base and having at least one pattern, a pad formed on at least a portion of the electrode layer, a light emitting diode positioned on the pad, and an adhesive layer formed on at least another portion of the electrode layer. The adhesive layer includes first and second adhesive layers each having a different adhesive strength.

Abstract: An exposure apparatus includes a polarizing member polarizing illumination light, and a filter having at least one opening. The polarizing member includes a first polarizing unit and a second polarizing unit arranged so as to surround the first polarizing unit. The second polarizing unit is configured so as to polarize the illumination light entering the second polarizing unit in the circumferential direction along the outer circumference of the first polarizing unit. At least a portion of the first polarizing unit is configured to polarize the illumination light in the direction orthogonal to the polarization direction in a part of the second polarizing unit located on the side opposite to the central part of the first polarizing unit. The openings are arranged in the filter so that the illumination light at the post stage of the filter and the polarizing member includes the illumination light polarized by the first and second polarizing units.

Abstract: A process of forming a metal-insulator-metal (MIM) capacitor is disclosed. The process includes steps of (i) forming an insulating film as a dielectric film of the MIM capacitor; (ii) forming a first portion of an upper electrode by a metal evaporation and a lift-off technique subsequent to the metal evaporation; and (iii) forming a second portion of the upper electrode by the metal evaporation and the lift-off technique subsequent to the metal evaporation for the second portion.

Abstract: In accordance with a method of manufacturing CZ silicon wafers, a parameter of at least two of the CZ silicon wafers is measured. A group of the CZ silicon wafers falling within a tolerance of a target specification is determined. The group of the CZ silicon wafers is divided into sub-groups taking into account the measured parameter. An average value of the parameter of the CZ silicon wafers of each sub-group differs among the sub-groups, and a tolerance of the parameter of the CZ silicon wafers of each sub-group is smaller than a tolerance of the parameter of the target specification. A labeling configured to distinguish between the CZ silicon wafers of different sub-groups is prepared. The CZ silicon wafers falling within the tolerance of the target specification are packaged.

Abstract: CMOS Ultrasonic Transducers and processes for making such devices are described. The processes may include forming cavities on a first wafer and bonding the first wafer to a second wafer. The second wafer may be processed to form a membrane for the cavities. Electrical access to the cavities may be provided.

Abstract: Disclosed herein is an apparatus for processing a substrate that forms a hole in a substrate while reducing a burr in the hole so that a module device can be inserted into the hole to reduce the thickness of a display device, and the display device using the apparatus. The apparatus for processing the substrate comprises a body configured to operably be rotatable, and a cylindrical cutting tip at an end of the body. The bottom surface of the cutting tip is in an acute angle with respect to a contact surface of the substrate to allow formation of a groove at the substrate.

Abstract: Semiconductor devices and methods of forming the same include forming a bottom source/drain region in a semiconductor substrate under a semiconductor fin. First charged spacers are formed on sidewalls of the semiconductor fin. A gate stack is formed on the fin, over the first charged spacers. Second charged spacers are formed on sidewalls of the fin above the gate stack. The fin is recessed to a height below a top level of the second charged spacers. A top source/drain region is grown from the recessed fin.

Abstract: A component includes a semiconductor body, a carrier, and a stabilization layer arranged between the semiconductor body and the carrier in the vertical direction. The semiconductor body has a first semiconductor layer facing away from the carrier, a second semiconductor layer facing the carrier, and an active layer arranged between the first semiconductor layer and the second semiconductor layer. The carrier has a first via and a second via laterally spaced apart from the first via by means of an intermediate region. The first via is connected to the first semiconductor layer in an electrically conductive manner and the second via is connected to the second semiconductor layer in an electrically conductive manner. The stabilization layer is continuous, overlaps with the vias in a top view, and laterally bridges the intermediate region. The stabilization layer is electrically insulated from the vias and from the semiconductor body.

Abstract: A display device according to an exemplary embodiment includes: a substrate including a pixel area and a transmission area adjacent to the pixel area; a transistor positioned on the substrate in the pixel area; a planarization layer positioned on the transistor in the pixel area; a wall positioned on the substrate between the pixel area and the transmission area; and a pixel electrode positioned on the planarization layer and extending in a trench between the planarization layer and the wall.

Abstract: A light-emitting device includes a substrate, first and second electrode pads, first to M-th light-emitting cells arranged in a line in a first direction between the first and second electrode pads, and first to N-th connection wires for electrically connecting the first to M-th light-emitting cells, wherein each of the first to M-th light-emitting cells comprises a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, wherein the first electrode pad is connected to the second conductive semiconductor layer of the first light-emitting cell while the second electrode pad is connected to the first conductive semiconductor layer of the M-th light-emitting cell, and an n-th connection wire electrically connects the first conductive semiconductor layer of an n-th light-emitting cell to the second conductive semiconductor layer of an (n+1)-th light-emitting cell, which are adjacent to each other.

Abstract: A semiconductor device may include a substrate, a first nanowire, a gate electrode, a first gate spacer, a second gate spacer, a source/drain and a spacer connector. The first nanowire may be extended in a first direction and spaced apart from the substrate. The gate electrode may surround a periphery of the first nanowire, and extend in a second direction intersecting the first direction, and include first and second sidewalls opposite to each other. The first gate spacer may be formed on the first sidewall of the gate electrode. The first nanowire may pass through the first gate spacer. The second gate spacer may be formed on the second sidewall of the gate electrode. The first nanowire may pass through the second gate spacer. The source/drain may be disposed on at least one side of the gate electrode and connected with the first nanowire. The spacer connector may be disposed between the first nanowire and the substrate.

Abstract: Provided herein are methods of tungsten nitride (WN) deposition. Also provided are stacks for tungsten (W) contacts to silicon germanium (SiGe) layers and methods for forming them. The stacks include SiGe/tungsten silicide (WSix)/WN/W layers, with WSix providing an ohmic contact between the SiGe and WN layers. Also provided are methods for reducing fluorine (F) attack of underlying layers in deposition of W-containing films using tungsten hexafluoride (WF6). Apparatuses to perform the methods are also provided.

Abstract: An embodiment comprises: a guide moving in the vertical direction or the horizontal direction; a transfer arm provided on the guide and loading spaced apart wafers; a laser emission unit disposed on the guide and emitting first laser beams at the spaced apart wafers loaded on the transfer arm; and a laser detection unit disposed below the transfer arm and collecting, from among the first laser beams, second laser beams having passed through gaps between the spaced apart wafers.

Abstract: A semiconductor device and method includes forming a conductive post on a die; coupling a test probe to the conductive post with solder; and etching the solder and the conductive post with a plurality of etching processes, the plurality of etching processes including a first etching process, the first etching process comprising etching the conductive post with a nitric-based etchant.