Abstract: One example describes a method of manufacturing Czochralski (CZ) silicon wafers. The method includes slicing an n-type CZ silicon ingot to form a plurality of CZ silicon wafers, determining a boron concentration of each CZ silicon wafer, dividing the CZ silicon wafers into sub-groups based on the boron concentration, wherein an average value of the boron concentration differs among the sub-groups, and labeling each sub-group of CZ silicon wafers with a different label which is indicative of the boron concentration.

Abstract: Capacitors and methods of forming the same include forming a dielectric layer on a first metal layer. The dielectric layer is oxygenated such that interstitial oxygen is implanted in the dielectric layer. A second metal layer is formed on the dielectric layer. The dielectric layer is heated to release the interstitial oxygen and to oxidize the first and second metal layers at interfaces between the dielectric layer and the first and second metal layers.

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The FinFET device structure also includes an epitaxial source/drain (S/D) structure formed over the fin structure. A top surface and a sidewall of the fin structure are surrounded by the epitaxial S/D structure. A first distance between an outer surface of the epitaxial S/D structure and the sidewall of the fin structure is no less than a second distance between the outer surface of the epitaxial S/D structure and the top surface of the fin structure.

Abstract: Semiconductor devices and methods of forming the same are provided. Semiconductor devices may include a plurality of gate electrodes that are stacked on a substrate and are spaced apart from each other in a vertical direction and a channel region extending through the plurality of gate electrodes in the vertical direction. Each of the plurality of gate electrodes may include a first conductive layer defining a recess recessed toward the channel region, and a second conductive layer in the recess defined by the first conductive layer. A first concentration of impurities in the second conductive layer may be higher than a second concentration of the impurities in the first conductive layer, and the impurities may include nitrogen (N).

Abstract: A mask for thin film deposition of a display apparatus having both end portions coupleable to a frame in a state of tension in a lengthwise direction thereof, the mask including: a first portion having a first thickness and a plurality of pattern holes through which a deposition material may pass; a second portion comprising a welding portion having a second thickness configured to be coupled to a frame; and a third portion connecting the first portion and the third portion, wherein the first thickness is less than the second thickness, and the third portion includes an inclined surface connecting the first portion and the second portion.

Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a second connection member disposed on the first connection member and the active surface of the semiconductor chip; a resin layer disposed on the encapsulant; and a rear redistribution layer embedded in the encapsulant so that one surface thereof is exposed by the encapsulant, wherein the resin layer covers at least portions of the exposed one surface of the rear redistribution layer, and the rear redistribution layer is electrically connected to the redistribution layer of the first connection member through connection members formed in first openings penetrating through the resin layer and the encapsulant.

Abstract: Fabrication of a heterostructure, such as a group III nitride heterostructure, for use in an optoelectronic device is described. The heterostructure can be epitaxially grown on a sacrificial layer, which is located on a substrate structure. The sacrificial layer can be at least partially decomposed using a laser. The substrate structure can be completely removed from the heterostructure or remain attached thereto. One or more additional solutions for detaching the substrate structure from the heterostructure can be utilized. The heterostructure can undergo additional processing to form the optoelectronic device.

Abstract: An organic light emitting display unit is disclosed, which includes: a substrate; a light shielding layer and a first electrode disposed on the substrate, the light shielding layer and the first electrode are disposed on a same layer and made of a same material.

Abstract: An organic thin film transistor includes a substrate, a source/drain layer that is located on the substrate and has a source region and a drain region, a first buffer layer that is located between the source region and the drain region, a semiconductor layer that is located on the source/drain layer and the first buffer layer, a gate insulating layer, and a gate electrode. The first buffer layer covers at least one portion of the source region and at least one portion of the drain region. The first buffer layer is located among the semiconductor layer, the source region, the drain region, and the substrate. The gate insulating layer covers the source/drain layer and the semiconductor layer. The gate electrode is located on the gate insulating layer, and a portion of the gate insulating layer is located between the gate electrode and the semiconductor layer.

Abstract: Structures for a field-effect transistor and methods for fabricating a structure for a field-effect transistor. A first epitaxial layer has a first surface and a second surface inclined relative to the first surface. A surface layer is arranged on the first and second surfaces of the first epitaxial layer. A second epitaxial layer is arranged over the surface layer on the first and second surfaces of the first epitaxial layer. A portion of the first epitaxial layer defines an interface with the surface layer. The portion of the first epitaxial layer contains a first concentration of a dopant. The surface layer contains a second concentration of the dopant that is greater than the first concentration of the dopant in the portion of the first epitaxial layer.

Abstract: A method for manufacturing a semiconductor device includes growing a first strained semiconductor layer on a substrate, the first strained semiconductor layer having a first type of strain, wherein the substrate comprises a first crystalline orientation at a top surface of the substrate, forming at least one trench in the substrate, wherein exposed sidewalls of the at least one trench have a second crystalline orientation different from the first crystalline orientation, growing a buffer layer in the at least one trench from the exposed sidewalls of the trench, and growing a second strained semiconductor layer on the buffer layer, the second strained semiconductor layer having a second type of strain, wherein the first type of strain is different from the second type of strain.

Abstract: Disclosed herein is an apparatus for processing a substrate that forms a hole in a substrate while reducing a burr in the hole so that a module device can be inserted into the hole to reduce the thickness of a display device, and the display device using the apparatus. The apparatus for processing the substrate comprises a body configured to operably be rotatable, and a cylindrical cutting tip at an end of the body. The bottom surface of the cutting tip is in an acute angle with respect to a contact surface of the substrate to allow formation of a groove at the substrate.

Abstract: In accordance with a method of manufacturing CZ silicon wafers, a parameter of at least two of the CZ silicon wafers is measured. A group of the CZ silicon wafers falling within a tolerance of a target specification is determined. The group of the CZ silicon wafers is divided into sub-groups taking into account the measured parameter. An average value of the parameter of the CZ silicon wafers of each sub-group differs among the sub-groups, and a tolerance of the parameter of the CZ silicon wafers of each sub-group is smaller than a tolerance of the parameter of the target specification. A labeling configured to distinguish between the CZ silicon wafers of different sub-groups is prepared. The CZ silicon wafers falling within the tolerance of the target specification are packaged.

Abstract: A semiconductor device may include a semiconductor element including a signal pad, an encapsulant encapsulating the semiconductor element and a lead including a first end located outside the encapsulant and a second end located within the encapsulant. The lead may be connected to the signal pad via a bonding wire within the encapsulant. The lead may include an upper surface extending from the first end to the second end. The upper surface may include a joined section where the bonding wire is joined and a rough section located within the encapsulant and having a higher surface roughness than the joined section. The rough section may be at least partly located lower than the joined section.

Abstract: A method for manufacturing a semiconductor device includes forming a conductive via extending vertically from a conductive layer, and depositing a first dielectric layer on the conductive layer and on lateral sides the conductive via. In the method, the conductive via is recessed with respect to a top surface of the first dielectric layer. An etch stop layer is deposited on the top surface of the first dielectric layer and on a top surface of the conductive via, and a second dielectric layer is deposited on the etch stop layer. The method also includes removing portions of the etch stop layer and the second dielectric layer to create a plurality of trenches spaced apart from each other. A trench of the plurality of trenches is formed over and exposes at least part of the conductive via, and a conductive material is deposited in the plurality of trenches.

Abstract: A doping system includes a light source to emit an optical pulse; a light source controller connected to the light source, to control an energy density of the optical pulse; and a beam adjusting unit to irradiate the optical pulse to a surface of a doping-object made of silicon carbide on which an impurity-containing source-film containing impurity atoms is deposited. The light source controller irradiates a first optical pulse to the impurity-containing source-film so as to form a reaction-product layer in the doping-object, and irradiates a second optical pulse having an energy density higher than an energy density of the first optical pulse, so as to introduce the impurity atoms into the target through the reaction-product layer.

Abstract: A method for manufacturing a transistor device includes forming a plurality of fins on a substrate, performing an annealing process to cause the fins to have a round shape, growing an epitaxial semiconductor layer on a surface of each fin, wherein the epitaxial semiconductor layer is formed along the round shape, and forming a gate structure on the substrate, wherein the gate structure is formed on the epitaxial semiconductor layer on the surface of each fin.

Abstract: In a method for manufacturing a semiconductor device, a substrate is provided. A dummy gate is formed on the substrate. A first dielectric layer is formed to peripherally enclose the dummy gate over the substrate. A second dielectric layer is formed to peripherally enclose the first dielectric layer over the substrate. The second dielectric layer and the first dielectric layer are formed from different materials. An implant operation is performed on the first dielectric layer to form a first doped portion in the first dielectric layer. The dummy gate is removed to form a hole in the first dielectric layer. An operation of removing the dummy gate includes removing a portion of the first doped portion to form the hole having a bottom radial opening area and a top radial opening area which is greater than the bottom radial opening area. A metal gate is formed in the hole.

Abstract: A light-emitting element according to an embodiment of the present document has a transparent electrode having an opening, and the transparent electrode has a protrusion on a side surface of the opening. A second electrode pad is arranged on the opening of the transparent electrode, and abuts the protrusion. Accordingly, peeling of the second electrode pad can be prevented, thereby improving the reliability of the light-emitting element.

Abstract: A semiconductor device has a substrate with a first opening and second opening formed in the substrate. A first semiconductor component is disposed on the substrate. The substrate is disposed on a carrier. A second semiconductor component is disposed on the carrier in the first opening of the substrate. A third semiconductor component is disposed in the second opening. The third semiconductor component is a semiconductor package in some embodiments. A first shielding layer may be formed over the semiconductor package. An encapsulant is deposited over the substrate, first semiconductor component, and second semiconductor component. A shielding layer may be formed over the encapsulant.