Abstract: A receiver (200) receives (402) a first signal including a sync portion (308) having a carrier acquisition segment (302) and a timing synchronization pattern (304), and a processing system (216) of the receiver calculates (404) a first plurality of squared magnitude Fourier transforms at a first plurality of frequencies on the carrier acquisition segment. The processing system derives (406) an initial carrier frequency error estimate by locating a peak in the first plurality of squared magnitude Fourier transforms, and corrects (408) the sync portion according to the initial carrier frequency error estimate, thereby producing a carrier-corrected sync portion. The processing system then removes (410) the timing synchronization pattern from the carrier-corrected sync portion, thereby producing a second signal having a residual carrier error.

Abstract: The invention relates to a reception method and a receiver. Mechanisms are used for generating, at each level, numbers relating to a bit 1 and a bit 2 and representing a probability of a transition metric of survivor paths. Mechanisms are used for separately summing the numbers relating to the bit 1 and the bit 0 of more than one state and representing the probability of the transition metric. Mechanisms are used for generating logarithms of the sums and means for generating a difference of the logic numbers relating to the bit 1 and the bit 0 representing the probability of the transition metric, whereby a received bit can be determined without a correct path tracing phase.

Abstract: The present invention is directed to a system and method that efficiently, accurately, and quickly detects a suitable stored fast retrain profile to permit the resumption of ADSL communications in the presence of changing line conditions in a dual POTS/ADSL communications system. The method of the present invention is based on measuring the amplitude and phase of a few discrete multi-tone tones in the receiver portion of a communications system and recording the number of times a profile is selected to replace a preceding profile. Broadly, the system and method of the present invention are realized by a digital signal processor that is configured to detect a fast retrain request, select a suitable stored profile, and apply the parameters associated with the selected profile to configure the customer premises modem.

Abstract: A method and cache for caching encoded symbols for a convolutional decoder with forward and backward recursion includes storing different encoded symbols of an encoded frame in each of a plurality of symbol memory elements (200, 202, 400) and routing the same encoded symbols from one of the plurality of symbol memory elements (200, 202, 400) to at least both a forward recursion decoder (208) and a backward recursion decoder (210, 402). The plurality of symbol memory elements may be, for example, single port RAM cells, each operatively controlled to receive different encoded symbols of an encoded frame as input. Control logic (204) routes the same encoded symbols from one of the plurality of symbol memory elements (200, 202, 400) to all of the recursion decoders (208, 210, 402).

Abstract: A method and apparatus for synchronizing ATM cells is disclosed. A synchronization unit receives a data clock signal and a plurality of control signals. Based on those signals, a sync pulse is generated. If synchronization is not achieved within a predetermined time period, the sync pulse is shifted one bit location. Through iterative shifting of the sync pulse, synchronization is ultimately achieved.

Abstract: A digital information reproducing apparatus and method in which a digital reproduction signal is equalized by predetermined equalizing characteristics, and a first clock signal is formed on the basis of the equalized signal. The digital reproduction signal is A/D converted using the first clock signal. A predetermined time base decompression is performed on the A/D converted signal every signal portion by the first clock signal and a second, lower frequency clock signal which is supplied separately from the first clock signal. Decoding data is output by performing a maximum likelihood decoding process to the signal after time base decompression. A predetermined time base compression is performed to the decoding data output by the maximum likelihood decoding process.

Abstract: A modem interface device is coupled to a computer such that the device is powered via a power signal received from a bus port of the computer, such as a Universal Serial Bus (USB) port, a RS-232 port, or a PS-2 port. The modem interface device has a telephone base connector, a modem connector, a power connector, a two-to-four-wire converter circuit, and a power distribution circuit. The two-to-four-wire converter circuit bidirectionally couples signals between the telephone base connector and the modem connector. The power distribution circuit receives electrical power from the power connector and supplies power to the two-to-four-wire converter circuit.

Abstract: The present invention concerns a receiver (110) including: an antenna (2) able to receive a frequency shift keying modulated signal (S), conversion means (3) able to receive this signal and to provide two first analog signals (I, Q); and demodulation means (112) able to receive said first signals and to provide a signal (X32+Y32) representative of the modulated signal. This receiver is characterised in that the demodulation means comprise: a complex filter (116) able to receive the first analog signals and to provide two second analog signals (X3, Y3), so that the gain of the transfer function (H3) can be equal to two different values (G1, G2); two normalisation means (118, 120) able to receive the second signals, and to provide in response two third analog signals (X32, Y32), representing a standard of the second signals; and an adder (122) able to receive said third signals and to provide the sum thereof.

Abstract: A spread spectrum diversity transmitter/receiver, in which a bit error rate is improved even at a severe multi path fading channel, is provided. At a transmitting section, a multi dimensional transmitting signal by code division is used not only for diversity itself but also for a convolutional encoding among diversity branches by a convolutional encoder. With this, an error correction function can be installed. At a receiving section, a Viterbi decoding is performed before a majority judgment is performed, a bit error at the front stage of a majority judging circuit is suppressed and the likelihood of the majority judgment is increased and consequently the bit error rate is largely improved.

Abstract: A spread spectrum clock generator comprising a spread spectrum modulation circuit and a control circuit. The spread spectrum modulation circuit may be configured to generate a clock signal in response to (i) a sequence of linearity ROM codes, (ii) a sequence of spread spectrum ROM codes, and (iii) a command signal. The control circuit may be configured to synchronize the command signal to a feedback signal. The sequence of linearity ROM codes and the sequence of spread spectrum ROM codes may be generated by predetermined mathematical formulas and optimized in accordance with predetermined criteria.

Abstract: A method and apparatus for recording time information for digital data streams. When a received digital data stream is recorded on a recording medium such as a digital video disk, time information for searching the digital data stream is added to the digital data stream, the format of the time information being compatible with the time format of the navigation data. The time information for the recorded digital data stream can be effectively used when searching a digital data stream corresponding to a search time requested by a user, thereby enabling fast and precise search operations with no additional information.

Abstract: A data processing system for the compression and decompression of data using Differential Pulse Code Modulation, and optimized for fast execution using a parallel processing DSP such as the Texas Instruments TMS320C8X family. Decompression is speeded up over the methods known in the art by combining the VLC codes and the additional interval bits into one code, which is then used as an index into a Look Up Table that yields the final result in one step instead of the multiple operations required by current implementations.

Abstract: The present invention provides independent CDR (clock and data recovery) functions on N number of high speed parallel channels, yet only requiring one capacitor. This enables multiple independent CDR channels to be integrated onto one IC with a minimum overhead component of one capacitor. In one embodiment, the present invention provides a multiple channel clock and data recovery system which includes N phase lock loop circuits for receiving in parallel N data channels, each of the N phase lock loop circuits including a digital phase detector and a dual-input VCO in which one VCO input is an analog input for setting the center frequency of the VCO and the other VCO input is a digital input from the respective phase detector for toggling the center frequency and wherein each phase detector compares the phase of the respective incoming data channel with that of the respective VCO output.