Abstract: A computer increases coverage in simulation of a design of a circuit by processing goals for coverage differently depending on whether or not the goals are on input signals of the circuit. Specifically, goals on input signals are used to automatically formulate constraints (“directly-derived constraints”) on values of input signals in test vectors. Goals on non-input signals (e.g. internal/output signals) are used with correlations to automatically formulate more additional constraints (“correlation-derived constraints”), by use of goals on non-input signals. The correlations indicate which non-input signals are associated with which input signals. The correlations are received from, for example, a human designer of the circuit. Depending on the embodiment, one or more of the automatically derived constraints are used with human-supplied constraints, to generate test vectors e.g. using a constraints solver, such as a satisfiability (SAT) engine.

Abstract: Methods and systems automate an approach to provide a way to convert a circuit design from a synchronous representation to an asynchronous representation without any designer or user interaction or redesign of the synchronous circuit. An optimized, automated, non-Interactive conversion of representations of synchronous circuit designs to and from representations of asynchronous circuit designs, facilitating traditional electronic design automation (EDA) tools to process and manipulate asynchronous designs while allowing synchronous designs to be implemented using asynchronous hardware solutions. The invention also facilitates feedback to synchronous design tools in synchronous representation for optimization and iteration of the design process by engineers, eliminating the need for engineers to be aware of the underlying asynchronous architecture of the underlying hardware implementation.

Abstract: A computer readable storage medium includes executable instructions to analyze an asynchronous, multi-rail digital circuit to identify a gating sub-circuit and a gated sub-circuit. The asynchronous, multi-rail digital circuit is transformed to segregate the gating sub-circuit and the gated sub-circuit.

Abstract: Disclosed are methods, systems and apparatus for automatically placing decoupling capacitors in an integrated circuit to compensate for voltage drops that might otherwise occur in a power grid. In one embodiment of the invention, the method includes generating one or more regions of the integrated circuit design, with each region having one or more cells, determining an amount of decoupling capacitance required in each region of the integrated circuit design by analyzing each cell in the region, and adding sufficient decoupling capacitor cells to the region to compensate for the potential voltage drop.

Abstract: A light intensity distribution simulation method for predicting an intensity distribution of light on a substrate when photomask including a pattern is irradiated with light in which a shape distribution of an effective light source is defined includes extracting plural point light sources from a shape distribution of the effective light source, entering the light emitted from each of the plural point light sources onto the pattern of the photomask, calculating an effective shape for each of the plural point light sources, the effective shape being a pattern obtained by excluding a part which is not irradiated with the light directly due to a sidewall of a pattern film including the pattern from a design shape of an aperture of the pattern, and calculating a distribution of diffraction light generated in the pattern for each of the plural point light sources by using the effective shape.

Abstract: A computer-implemented method of placing input/output (I/O) pins of a circuit design for an integrated circuit (IC) can include selecting a bus from a plurality of buses, where the selected bus includes a plurality of I/O pins and is part of an interface, and, for each of a plurality of banks of the IC, determining a cost of assigning the selected bus to the bank according, at least in part, to a measure of proximity of the bank to another bank including a bus of the interface. The method can include selecting an available bank having a lowest cost, assigning at least one of the plurality of I/O pins of the selected bus not assigned to a bank of the IC to the selected bank, and outputting a circuit design including an association of I/O pin(s) of the selected bus to the selected bank.

Abstract: A method for performing a static timing analysis on a circuit that includes gates and their respective interconnects by incorporating the effect of Miller capacitance on timing. A primitive gate is selected with its respective fan-out gates, interconnects attached to the primitive gate's output and interconnects attached to the output of each respective fan-out gate are determined. Using a metric, it is determined if the Miller capacitance effect of a CMOS gate on timing of its fan-out gate and interconnect timing is significant for each fan-out gate. If yes, the gate is replaced with a nonlinear driver model. If no, the gate is replaced with a fixed or dynamic capacitance. Next, if at least one of the fan-out gates is replaced with the nonlinear driver model, the primitive gate is likewise replaced with its corresponding nonlinear model as well.

Abstract: An integrated circuit comprises digital circuitry having at least one digital logic cell and at least one skew adjusting cell. The skew adjusting cell is configured to adjust the skew of a signal in the digital circuitry of the integrated circuit to a desired amount. The digital logic cell and the skew adjusting cell are selected from a cell library.

Abstract: A chip layout is generated based on a quantified fabrication process capability. A minimum required value is selected for a fabrication process capability factor associated with a fabrication process to be performed on a layer sub-region within the chip. Design rules are determined for the layer sub-region within the chip that will enable the selected minimum required value for the fabrication process capability factor associated with the layer sub-region to be satisfied. A layout is then generated for the layer sub-region within the chip using the determined design rules associated with the layer sub-region. Fabrication process capability can be improved by restricting the design rules and generated layouts to a linear design style that requires features defined within the chip to be linear in shape and without bends. The linear design style enables optimization of photolithographic rendering without the need to consider two-dimensional optical effects.

Abstract: A sequence-pair creating apparatus includes a block placement storing unit that stores information of size of a block bi in a block set B and information of block placement, creates a sequence-pair (P, M), serving as a pair of a sequence P and a sequence M of the block bi, and further includes a binary relation setting unit that sets, in accordance with the information of block placement and information of size, a binary relation serving as an order relation that indicates a relative configuration between the blocks of a block pair of two blocks and that is derived from a configuration constraint between the blocks extracted from the information of block placement and information of size or designated by an external input, and a total order relation setting unit that sets a series of ranks of the sequences P and M for all the blocks on the basis of the information of block placement and information of size so as to satisfy all binary relations set by the binary relation setting unit.

Abstract: A method and apparatus are described for determining an accurate yield prediction for an integrated circuit by combining conventional yield loss analysis (such as extracted from physical dimension information concerning a circuit layout) with extracted electrical sensitivity and/or functional sensitivity information for circuit elements (such as nets connecting logic blocks or other signal lines) to obtain an actual performance-based probability of failure (POF) for the overall circuit.

Abstract: An improved method, system, and article of manufacture for reducing via failures is described. In one approach, additional vias or via cuts are inserted into an IC device to increase the number of cuts in a given area. The additional vias or via cuts are inserted until a sufficient via density level has been reached.

Abstract: In one embodiment, a method for verifying one or more particular properties of a circuit using a learning strategy to determine suitable values of particular verification parameters includes classifying each of multiple properties of a circuit according to circuit size and selecting a candidate property from the properties. The candidate property set includes one or more particular properties from each property class. The method also includes attempting to verify one or more particular properties of the circuit using the candidate property set and particular values of particular verification parameters. The method also includes determining suitable values of the particular verification parameters according the attempted verification of the particular properties of the circuit using the candidate property set and the particular values of the particular verification parameters.

Abstract: A method, computer-readable medium, and system for performing data preparation are provided. An integrated circuit design is received, and a plurality of pre-optical proximity correction processes are invoked such that the plurality of pre-optical proximity correction processes are performed in parallel. An optical proximity correction process is invoked in response to a determination that each of the plurality of pre-optical proximity correction processes have completed. A post-optical proximity correction process is invoked in response to a determination that the optical proximity correction process has completed.

Abstract: A technique for determining, without having to perform optical proximity correction, when the result of optical proximity correction will fail to meet the design requirements for printability. A disclosed embodiment has application to a process for producing a photomask for use in the printing of a pattern on a wafer by exposure with optical radiation to optically image the photomask on the wafer. A method is set forth for checking the printability of a target layout proposed for defining the photomask, including the following steps: deriving a system of inequalities that expresses a set of design requirements with respect to the target layout; and checking the printability of the target layout by determining whether the system of inequalities is feasible.

Abstract: Methods of independently migrating a hierarchical design are disclosed. A method for migrating a macro in an integrated circuit comprises: determining an interface strategy between a base cell in the macro and the macro, the base cell including an interface element involved in the interface strategy; migrating the base cell independently with respect to the macro based on the interface strategy; initially scaling the macro; swapping the migrated base cell into the macro; and legalizing content of the initially scaled macro.

Abstract: A method, system and computer program product for determining aggressor-induced crosstalk in a victim net of a stage of an integrated circuit design is provided. The methodology can include combining a plurality of aggressor nets to construct a virtual aggressor net, determining a current waveform induced on the victim net by the plurality of small aggressor nets, and modeling a current waveform induced by the virtual aggressor on the victim net based on the contribution of the current waveforms determined for the plurality of small aggressor nets. In a further embodiment, the methodology can also comprise evaluating an effect of an aggressor net on a victim net; and including that aggressor net in the virtual aggressor net if its effect is below a predetermined threshold. The effect evaluated by the methodology can, for example, be the height of a glitch induced on the victim net by a transition in the aggressor net.

Abstract: A computer-implemented method of performing a Computer-Aided Design (CAD) flow on a circuit design for a programmable logic device (PLD) can include inserting a preprocessing task into the CAD flow prior to a selected task that does not recognize a constraint, wherein the preprocessing task introduces a modification into the circuit design according to the constraint. The circuit design including the modification can be processed through the selected task of the CAD flow. A reversal task can also be inserted into the CAD flow, wherein the reversal task removes the modification introduced into the circuit design by the preprocessing task. The method further can include processing the circuit design through at least one other task of the CAD flow and outputting the processed circuit design.

Abstract: A method and system for maintaining synchronization between a plurality of layout clones of an integrated circuit design, wherein each layout clone comprises at least one figure. The method comprises tracking relationships between equivalent figures of the plurality of layout clones, wherein the plurality of layout clones are associated with one another within an equivalence group and propagating an edit made in one of the layout clones within an equivalence group to the other layout clones within the equivalence group.

Abstract: A method and an apparatus for creating a representation of a circuit with a pipelined loop from an HDL source code description. It infers a circuit including a pipelined loop which has cycle level simulation behavior matching that of the source HDL. Loop carry dependencies and memory and signal I/O accesses within the loop are scheduled correctly.