Patents Examined by Leonard Chang
  • Patent number: 9487060
    Abstract: An air conditioning control apparatus for a vehicle includes a call monitor that monitors a phone call in the vehicle; a timer that counts a preset time; a driver that adjusts an air volume of an air conditioning apparatus in the vehicle; and a controller that controls the driver to set the air volume of the air conditioning apparatus as a reference value if the call monitor recognizes the occurrence of a phone call, and control the driver to increase the air volume of the air conditioning apparatus up to a user setting value in order from a low level to a high level if the phone call is maintained during the preset time.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: November 8, 2016
    Assignee: Hyundai Motor Company
    Inventor: Hyunwoo Choi
  • Patent number: 9157629
    Abstract: A lighted hand tool includes a cylindrical-shaped rivet member, and a first and second tool member each having a handle, a jaw, and a pivot portion therebetween. A cylindrical bore section is defined by each pivot portion, and each bore is in co-axial alignment for aligned receipt of the rivet member therein. The rivet member prevents lateral separation of the first and second hand tool therebetween, while enabling pivotal movement of the jaw portions. An illumination device is formed for sliding receipt in the receiving channel of the rivet member, and aligns an output portion with the communication port to illuminate the work area. A first end cap and second cap are threadably disposed in the opposite openings into the rivet member. The first and second end cap cooperate to securely abut and seat the illumination device therebetween.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: October 13, 2015
    Assignee: ReadyMax, Inc.
    Inventors: Bill E. Brauner, Eivind Clausen, Mickey Makay
  • Patent number: 8980742
    Abstract: Provided are methods and apparatuses for manufacturing a multilayer metal thin film without additional heat treatment processes. The method of manufacturing a multilayer metal thin film including steps of: (a) forming a first metal layer on a substrate by flowing a first metal precursor into a first reaction container; and (b) forming a second metal layer on the first metal layer by flowing a second metal precursor into a second reaction container, wherein the step (b) is performed in a range of a heat treatment temperature of the first metal layer so that the second metal layer is formed as the first metal layer is heat-treated.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: March 17, 2015
    Assignee: Wonik IPS Co., Ltd.
    Inventors: Jung Wook Lee, Young Hoon Park
  • Patent number: 8962460
    Abstract: Methods of selectively forming a metal-doped chalcogenide material comprise exposing a chalcogenide material to a transition metal solution, and incorporating transition metal of the transition solution into the chalcogenide material without substantially incorporating the transition metal into an adjacent material. The chalcogenide material is not silver selenide. Another method comprises forming a chalcogenide material adjacent to and in contact with an insulative material, exposing the chalcogenide material and the insulative material to a transition metal solution, and diffusing transition metal of the transition metal solution into the chalcogenide material while substantially no transition metal diffuses into the insulative material.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Jerome A. Imonigie, Prashant Raghu, Theodore M. Taylor, Scott E. Sills
  • Patent number: 8946051
    Abstract: It is an object to provide a method for manufacturing an SOI substrate in which crystal defects of a single crystal semiconductor layer are reduced even when a single crystal semiconductor substrate in which crystal defects exist is used. Such an SOI substrate can be manufactured through the steps of forming a single crystal semiconductor layer which has an extremely small number of defects over a single crystal semiconductor substrate by an epitaxial growth method; forming an oxide film on the single crystal semiconductor substrate by thermal oxidation treatment; introducing ions into the single crystal semiconductor substrate through the oxide film; bonding the single crystal semiconductor substrate into which the ions are introduced and a semiconductor substrate to each other; causing separation by heat treatment; and performing planarization treatment on the single crystal semiconductor layer provided over the semiconductor substrate.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: February 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Eriko Nishida
  • Patent number: 8927314
    Abstract: A method of manufacturing a solar cell includes the steps of: providing a substrate having a front side, a back side and a doped region; forming a conductor layer on the front side; firing the conductor layer at a temperature such that the conductor layer is formed with a first portion embedded into the doped region and a second portion other than the first portion; forming an anti-reflection coating (ARC) layer on the front side and the second portion, wherein the ARC layer covers the conductor layer so that the second portion of the conductor layer is disposed in the ARC layer; and removing the ARC layer on the conductor layer so that the conductor layer has an exposed surface exposed out of the ARC layer, wherein the exposed surface of the conductor layer is substantially flush with a first exposed surface of the ARC layer.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: January 6, 2015
    Assignee: Big Sun Energy Technology Inc.
    Inventors: Sheng Yung Liu, Chin-Tien Yang, Chun-Hung Lin
  • Patent number: 8922002
    Abstract: Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: December 30, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Young Do Kweon, Tongbi Jiang
  • Patent number: 8912077
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The semiconductor wafer is supported by a substrate carrier. The mask is then patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits while supported by the substrate carrier.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: December 16, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Saravjeet Singh, Brad Eaton, Ajay Kumar, Wei-Sheng Lei, James M. Holden, Madhava Rao Yalamanchili, Todd J. Egan
  • Patent number: 8912102
    Abstract: A system for and method of processing an article such as a semiconductor wafer is disclosed. The wafer includes first and second surfaces which are segmented into a plurality of first and second zones. The first surface of the wafer, for example, on which devices or ICs are formed is processed by, for example, laser annealing while the second surface is heated with a backside heating source. Corresponding, or at least substantially corresponding, zones on the first and second surfaces are processed synchronously to reduce variations of post laser anneal thermal budget across the wafer.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: December 16, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Chyiu Hyia Poon, Alex K H See, Meisheng Zhou
  • Patent number: 8906756
    Abstract: An object is to provide a semiconductor device including an oxide semiconductor, which has stable electrical characteristics and high reliability. In a manufacturing process of a bottom-gate transistor including an oxide semiconductor layer, heat treatment in an atmosphere containing oxygen and heat treatment in vacuum are sequentially performed for dehydration or dehydrogenation of the oxide semiconductor layer. In addition, irradiation with light having a short wavelength is performed concurrently with the heat treatment, whereby elimination of hydrogen, OH, or the like is promoted. A transistor including an oxide semiconductor layer on which dehydration or dehydrogenation treatment is performed through such heat treatment has improved stability, so that variation in electrical characteristics of the transistor due to light irradiation or a bias-temperature stress (BT) test is suppressed.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: December 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Ryosuke Watanabe, Suzunosuke Hiraishi, Junichiro Sakata
  • Patent number: 8883577
    Abstract: A semiconductor device manufacturing method includes forming a fin region over a substrate, forming a dummy gate electrode over the fin region, forming a first insulating film over the dummy gate electrode and the fin region, polishing the first insulating film until the dummy gate electrode is exposed, removing part of the exposed dummy gate electrode to form a trench, forming a gate insulator over the surface of the fin region exposed in the trench, and forming a gate electrode over the gate insulator.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: November 11, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yasuo Nara
  • Patent number: 8883619
    Abstract: A method for manufacturing a semiconductor device includes the steps of: preparing a substrate made of silicon carbide; forming, on one main surface of the substrate, a detection film having a light transmittance different from that of silicon carbide; confirming presence of the substrate by applying light to the detection film; and forming an active region in the substrate whose presence has been confirmed.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: November 11, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideto Tamaso, Hiromu Shiomi
  • Patent number: 8883644
    Abstract: Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n?2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n?1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n?1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: November 11, 2014
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, Mirzafer K. Abatchev
  • Patent number: 8853045
    Abstract: A precision low capacitance resistor is formed, e.g., in a bulk substrate. An embodiment includes forming a source/drain region on a substrate, patterning a portion of the source/drain region to form segments, etching the segments to substantially separate an upper section of each segment from a lower section of each segment, and filling the space between the segments with an insulating material. The resulting structure maintains electrical connection between the segments at end pads, but separates the resistor segments from the bottom substrate, thereby avoiding capacitive coupling with the substrate.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: October 7, 2014
    Assignee: GlobalFoundries, Inc.
    Inventor: Steven R. Soss
  • Patent number: 8846496
    Abstract: To provide a method of obtaining a single crystal semiconductor film by a method that is simple and low-cost. A single crystal semiconductor film 11 having compression stress is formed over a surface of a single crystal semiconductor substrate 10 by a vapor phase epitaxial growth method, a film having tensile stress (for example, a thermo-setting resin film 12) is formed over a surface of the single crystal semiconductor film 11, and the single crystal semiconductor substrate 10 and the single crystal semiconductor film 11 are separated from each other by a separation step in which force is applied to the single crystal semiconductor film 11, thereby obtaining a single crystal semiconductor film. Note that as the thermo-setting resin film 12, an epoxy resin film can be used, for example.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: September 30, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Sho Kato, Kazutaka Kuriki
  • Patent number: 8846456
    Abstract: A substrate which has at least one component, such as a semiconductor chip, arranged on it is manufactured from a film made of plastic material laminated onto a surface of the substrate and of the at least one component, where the surface has at least one contact area. First, the film to be laminated onto the surface of the substrate and the at least one component, or a film composite including the film, is arranged in a chamber such that the chamber is split by the film or film composite into a first chamber section and a second chamber section, which is isolated from the first chamber section so as to be gastight. A higher atmospheric pressure is provided or produced in the first chamber section than in the second chamber section; and contact is made between the surface of the substrate arranged in the second chamber section and the at least one component and the film or the film composite, which contact brings about the lamination of the film onto the surface.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: September 30, 2014
    Assignee: Siemens Aktiengesellschaft
    Inventor: Karl Weidner
  • Patent number: 8828877
    Abstract: The present invention provides an etching solution less affected by trench structures and also provides an isolation structure-formation process employing the solution. The etching solution contains hydrofluoric acid and an organic solvent. The organic solvent has a ?H value defined by Hansen solubility parameters in the range of 4 to 12 inclusive and the saturation solubility thereof in water is 5 wt % or more at 20° C. This solution can be adopted instead of known etching solutions used in conventional production processes of semiconductor elements.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: September 9, 2014
    Assignee: AZ Electronic Materials USA Corp.
    Inventor: Issei Sakurai
  • Patent number: 8802492
    Abstract: Methods for producing RRAM resistive switching elements having reduced forming voltage include doping to create oxygen deficiencies in the dielectric film. Oxygen deficiencies in a dielectric film promote formation of conductive pathways.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: August 12, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Jinhong Tong, Randall Higuchi, Imran Hashim, Vidyut Gopal
  • Patent number: 8803217
    Abstract: An electronic device including a nonvolatile memory cell can include a substrate including a first portion and a second portion, wherein a first major surface within the first portion lies at an elevation lower than a second major surface within the second portion. The electronic device can also include a charge storage stack overlying the first portion, wherein the charge storage stack includes discontinuous storage elements. The electronic device can further include a control gate electrode overlying the first portion, and a select gate electrode overlying the second portion, wherein the select gate electrode includes a sidewall spacer. In a particular embodiment, a process can be used to form the charge storage stack and control gate electrode. A semiconductor layer can be formed after the charge storage stack and control gate electrode are formed to achieve the substrate with different major surfaces at different elevations. The select gate electrode can be formed over the semiconductor layer.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: August 12, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Rajesh A. Rao, Ramachandran Muralidhar
  • Patent number: 8766412
    Abstract: A semiconductor chip has devices formed on a first principal plane of a semiconductor substrate, wherein a second principal plane of the semiconductor substrate is planarized, and an organic film having plus charges on an outer side is provided on the second principal plane.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: July 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Manabu Matsumoto