Patents Examined by Linh My Nguyen
  • Patent number: 7071743
    Abstract: A phase-locked loop (“PLL”) for use in a programmable logic device (“PLD”) is constructed with modular components, which may be digital, and which may be programmable or adjustable, in place of the conventional analog charge pump and loop filter. Connections are provided between those components and the remainder of the PLD so that if the PLL is not being used in a particular user design of the PLD, the PLL modular components may be used by other portions of the PLD. Similarly, those connections allow other portions of the PLD to be used in place of one or more of the modular components where more complex or special filtering than can be provided by the modular components is required.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: July 4, 2006
    Assignee: Altera Corporation
    Inventor: Gregory Starr
  • Patent number: 7064617
    Abstract: Temperature compensation is achieved by adjusting a divide ratio of a multi-modulus divider circuit in a feedback path of a phase-locked loop based on the detected temperature. The divide ratio is adjusted based on stored adjustment values stored in non-volatile memory. Interpolation may be used to interpolate between the stored adjustment values.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: June 20, 2006
    Assignee: Silicon Laboratories Inc.
    Inventors: Jerrell P. Hein, Axel Thomsen
  • Patent number: 7064632
    Abstract: A microwave circuit comprises a printed circuit board (PCB) on which is fabricated a circuit including passive components such as filters (40) formed by printed conductive patterns. In order to enhance the performance of the circuit, selected components such as filters are made with a greater precision on substrate material (41), such as alumina, having a higher dielectric constant than that of the printed circuit board material. The finished component is mounted on the printed circuit board and the conductive pattern is connected by wire bonds (48, 50) to microstrip tracks (51) of the printed circuit board.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: June 20, 2006
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Christopher M. Buck, Keith R. Williams
  • Patent number: 7064592
    Abstract: A method of setting a delay offset in slave Delay-Locked Loop (DLL) modules by a master DLL module is disclosed. The method includes determining whether a delay tap value needs to be adjusted based on a comparison with a reference clock signal, calculating a delay offset value to correct the delay tap value, repeating the determining and calculating steps a predetermined number of times and forwarding a representative value of the calculated delay offset values. The representative value is determined through a comparison between all of the calculated delay offset values obtained in the repeating step.
    Type: Grant
    Filed: May 14, 2004
    Date of Patent: June 20, 2006
    Assignee: Broadcom Corporation
    Inventor: Yong H. Jiang
  • Patent number: 7061277
    Abstract: A differential-to-single-ended (DSE) converter receives a positive differential input and a negative differential input and generates a single-ended output. The DSE converter comprises: 1) a first comparator having a non-inverting input coupled to the positive differential input and an inverting input coupled to the negative differential input; 2) a second comparator having an inverting input coupled to the positive differential input and a non-inverting input coupled to the negative differential input; 3) a first D flip-flop having a Logic 1 input and clocked by a rising edge on the first comparator output; 4) a second D flip-flop having a Logic 1 input and clocked by a rising edge on the second comparator output; and 5) a latch circuit having a first input coupled to the first D flip-flop output and a second input coupled to the second D flip-flop output. Rising edges on the first and second D flip-flop outputs cause the latch output to change state.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: June 13, 2006
    Assignee: National Semiconductor Corporation
    Inventor: Jane Xin-LeBlanc
  • Patent number: 7057426
    Abstract: A frequency converter comprising a variable gain amplifier which amplifies the local oscillation signal according to a gain control signal and outputs an amplified local signal, an even harmonic mixer which is supplied with an input signal and an amplified local oscillation signal and outputs an output signal whose frequency is a sum of a first frequency of the input signal and a second frequency of two or more even numbered times a frequency of the amplified local oscillation signal, an amplitude detector which is supplied with the amplified local oscillation signal and outputs a direct current signal having an amplitude corresponding to an amplitude of the amplified local oscillation signal, and a comparator which compares the direct current signal of the amplitude detector with the reference direct current signal to generate an output signal as the gain control signal.
    Type: Grant
    Filed: July 21, 2003
    Date of Patent: June 6, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takafumi Yamaji, Osamu Watanabe
  • Patent number: 7057429
    Abstract: An apparatus and method for generating phase related clocks, includes delaying a clock input by a cycle delay magnitude to generate a cycle delay signal and N delay taps is disclosed. Each delay tap has a delay equal to a fractional amount of the cycle delay magnitude. The method further includes delaying the clock input by an alignment magnitude to generate a first aligned phase signal and delaying each of the N delay taps by fractional amounts of the alignment magnitude to generate N phase aligned signals. A feedback loop is closed by a phase comparison between the first aligned phase signal and the cycle delay signal. The phase comparison result is used to adjust the cycle delay magnitude, which adjusts delays of the cycle delay signal and the N delay taps, and adjust the alignment magnitude, which adjust delays of the first aligned phase signal and the N phase aligned signals.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: June 6, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Kang Yong Kim
  • Patent number: 7057453
    Abstract: Method and system for reducing parasitic feedback and resonances in high-gain transimpedance amplifiers. In a first embodiment of the present invention, a resistive layer is implemented in the gaps of a high-gain transimpedance amplifier's metallic planes. In a second embodiment of the present invention, a resistive layer is implemented underneath a high-gain transimpedance amplifier's ground plane, vias are implemented to create contact between the resistive layer and the ground plane.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: June 6, 2006
    Assignee: Inphi Corporation
    Inventors: Tom Peter Edward Broekaert, Marian Pospieszalski
  • Patent number: 7055125
    Abstract: A programmable logic array (PLA) in accordance with the invention achieves a maximum amount of depopulation of programmable connections while still implementing a logic function and maintaining flexibility for future reprogramming. In addition, a PLA in accordance with the invention can be built so that no matter what functionality is programmed, performance characteristics for the device are maintained. Further, a PLA in accordance with the invention does not require a regular array structure.
    Type: Grant
    Filed: April 5, 2001
    Date of Patent: May 30, 2006
    Assignee: Lightspeed Semiconductor Corp.
    Inventors: Robert Osann, Jr., Patrick Hallinan, Jung Lee, Shridhar Mukund
  • Patent number: 7049856
    Abstract: Various methods and circuits for implementing high speed peak amplitude comparison. The invention achieves higher speed of operation by eliminating the slow feedback loop commonly employed in peak detection. In one embodiment, the invention directly compares a signal that represents the peak amplitude of the input signal minus a small voltage drop, to a modified reference voltage. The modified reference voltage corresponds to the reference voltage that is adjusted to compensate for the small voltage drop in the maximum input voltage. In another embodiment, the invention implements a differential version of the peak amplitude comparator to obtain better noise rejection and reduced effective offset among other advantages.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: May 23, 2006
    Assignee: Broadcom Corporation
    Inventors: Afshin Momtaz, Wee-Guan Tan, Armond Hairapetian
  • Patent number: 7049864
    Abstract: A digital frequency divider apparatus includes a plurality of next-state generator elements receiving an input clock signal thereto, and configured to generate a next value for each of a corresponding plurality of internal state variables. A plurality of flip-flop elements is configured to store the generated next values for the plurality of internal state variables, the plurality of flip-flop elements further configured to provide a present value of the plurality of internal state variables to the next-state generator elements through a feedback path therebetween. The generated next values for the plurality of internal state variables are based upon the present values of the plurality of internal state variables and the input clock signal.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: May 23, 2006
    Assignee: International Business Machines Corporation
    Inventors: Ram Kelkar, Pradeep Thiagarajan
  • Patent number: 7046061
    Abstract: Disclosed are a delay locked loop (DLL) and a method of driving the same. The delay locked loop includes a clock buffer for buffering an inputted external clock to generate an internal clock, the clock buffer generating a control signal for disabling the internal clock depending on whether the power is down, a delayed line for delaying the internal clock, a clock driver for buffering the output of the delayed line to generate a clock signal, the clock driver disabling the clock signal depending on whether the power is down, a delay monitor for delaying the external clock, a phase detector for detecting the difference in a phase between the internal clock and the output of the delayed monitor to generate a detected signal, the phase detector being disabled according to the control signal, and a shift register for controlling the delayed line according to the detected signal from the phase detector.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: May 16, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jong Tae Kwak
  • Patent number: 7046066
    Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a gated clock signal in response to (i) a write enable signal and (ii) a system clock signal. The gated clock signal is pulsed active while the write enable signal is active. The second circuit may be configured to generate the write enable signal.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: May 16, 2006
    Assignee: Via Telecom Co., Ltd.
    Inventors: Alon Saado, Linley M. Young, Muhammad Afsar
  • Patent number: 7046065
    Abstract: A programmable clock generator delivers, using a primary clock signal of determined frequency, a first clock signal the frequency of which is equal to the frequency of the primary clock signal divided by a set point M. The set point M is a decimal number comprising a whole part M1 and a decimal part M2 and the clock generator modulates the period of the pulses of the first clock signal so that the duration of Ni successive pulses is substantially equal to M*Ni times the period of the primary clock signal, Ni being a reference number for modulating the period of the pulses of the first clock signal.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: May 16, 2006
    Assignee: STMicroelectronics S.A.
    Inventors: Ludovic Ruat, Dragos Davidescu
  • Patent number: 7046056
    Abstract: An integrated circuit device having a select circuit, a summing circuit and a phase mixer. The select circuit selects one of a plurality of offset values as a selected offset. The summing circuit sums the selected offset with a phase count value, the phase count value indicating a phase difference between a reference clock signal and one of a first plurality of clock signals. The phase mixer combines the first plurality of clock signals in accordance with the sum of the selected offset and the phase count value to generate an output clock signal.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: May 16, 2006
    Assignee: Rambus Inc.
    Inventors: Jade M. Kizer, Benedict C. Lau, Craig E. Hampel
  • Patent number: 7046069
    Abstract: Modularized clock decoupling and signal delay management is provided for the purpose of reducing simultaneous binary signal switch-induced inductive voltage transients in lower voltage synchronous semiconductor devices. The voltage levels in low-voltage devices must be tightly maintained for proper transistor logic operations. Signal switching results in current changes on the power net of an IC. Current changes produce inductive voltage transients which propagate throughout the device and which can interfere with signal transmission and device operation. Relatively independent functioning circuits of an integrated circuit are isolated from the chip clock and each isolated circuit module is provided with its own independent, same-frequency, but slightly out-of-phase clock signal. Signal switching within any module is thus occurring out-of-phase with that of all other modules and, as a result, switch-associated voltage transients are limited to those associated with one module's circuits at a time.
    Type: Grant
    Filed: July 19, 2004
    Date of Patent: May 16, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Keith Gerard Krasnansky, Ronald Drafz
  • Patent number: 7042265
    Abstract: For control, some memory circuits use a delay-locked loop to generate a set of signals, each delayed a different amount relative a reference signal. However, as circuits get faster and faster, conventional delay-locked loops require use of extra interpolation circuitry to generate smaller delays, and thus consume considerable power and circuit space. Accordingly, the inventor devised a circuit which interlaces and synchronizes two delay-locked loops, each including a number of controllable delay elements linked in a chain. In one embodiment, the first loop produces a sequence of clock signals delayed an even number of delay periods relative a reference clock signal, and the second loop produces a sequence of clock signals delayed an odd number of delay periods relative the reference clock signal. In addition, the first and second loops are synchronized.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: May 9, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Ronnie M. Harrison
  • Patent number: 7042255
    Abstract: Programmable differential capacitance is implemented in equalization circuits. The programmable differential capacitance improves the common mode rejection ratio of circuits processing differential signals of various frequencies and voltage swings. Multiple capacitance devices provide the programmable capacitance, which provides an equalization circuit with different, selectable (i.e., programmable) values of capacitance for boosting the transition speed and strength of differential signals processed by the equalization circuit.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: May 9, 2006
    Assignee: Altera Corporation
    Inventor: Simar Maangat
  • Patent number: 7042259
    Abstract: A clock generating apparatus is provided that includes a first phase lock loop device powered by an analog (or fixed) power supply voltage and a second phase lock loop device powered by the analog power supply voltage and a digital power supply voltage. The second phase lock loop device to output a clock signal having an adaptive frequency based on the digital power supply voltage.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: May 9, 2006
    Assignee: Intel Corporation
    Inventors: Nasser A. Kurd, Javed S. Barkatullah, Paul Madland
  • Patent number: 7038507
    Abstract: A frequency synthesizer is disclosed. According to one embodiment, the frequency synthesizer includes a phase locked loop (PLL) having an analog mixer phase detector and an auxiliary digital frequency detector coupled to the phase locked loop. The PLL may include a programmable divider having an input terminal responsive to an output signal of the frequency synthesizer and having an output terminal coupled to an input terminal of the analog mixer phase detector, a loop filter having an input terminal coupled to an output terminal of the analog mixer phase detector, and a voltage controlled oscillator having a control terminal coupled to an output terminal of the loop filter. The programmable divider may include a direct digital synthesizer.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: May 2, 2006
    Assignee: Teledyne Technologies Incorporated
    Inventor: Anthony David Williams