Abstract: A charge pump includes a current source capable of generating a reference current. The charge pump also includes a first current mirror capable of conducting a first current. The charge pump further includes a second current mirror capable of conducting a second current and the reference current. In addition, the charge pump includes an output coupled to the first and second current mirrors and capable of providing one of the first and second currents as an output of the charge pump. The first current mirror may be capable of conducting the first current and a second reference current. The second current mirror may be capable of conducting the second current, the reference current, and the second reference current.

Abstract: A circuit for horizontal deflection includes a first PLL circuit that is arranged to provide a first PLL output signal, and a second PLL circuit that is arranged to provide a second PLL output signal. A first PLL circuit is arranged to provide equalizing pulse removal. The first PLL circuit includes a gated PFD and an equalization pulse removal logic circuit. The equalization pulse removal logic circuit is arranged such that, if equalizing pulses occur in a sync signal, the gated PFD is gated during each equalizing pulse. The second PLL circuit is arranged to provide a wide capture range, and to lock a center of a pulse of the center of the feedback signal with the leading edge of the first PLL output signal. The second PLL circuit includes a frequency comparator circuit, a PFD, and a phase detector. The frequency comparator circuit is arranged to select either the PFD or the phase detector.

Abstract: The rising edge triggered flip-flops and falling edge triggered flip-flops in one or more clock domains of a target system can be simultaneously initialized to predetermined logic states by activating the flip-flop set/clear inputs, freezing the flip-flop clock signals high or low, subsequently deactivating the flip-flop set/clear inputs, and then re-enabling the clock signals.

Abstract: A programmable logic device includes configurable phase-locked loop (PLL) circuitry that outputs multiple clock signals having programmable phases and frequencies. Each output signal is programmably selectable for use as an external clock, internal global clock, internal local clock, or combinations thereof. The PLL circuitry has programmable frequency dividing, including programmable cascaded frequency dividing, and programmable output signal multiplexing that provide a high degree of clock design flexibility.

Abstract: A system and method to establish the lock point of a digital synchronous circuit (e.g., a DLL) at the center of or close to the center of its delay line is disclosed. The synchronous circuit is configured to selectively use either a reference clock or its inverted version as the clock signal input to the delay line based on a relationship among the phases of the reference clock, the inverted reference clock, and a feedback clock (generated at the output of the delay line). A delayed version of the feedback clock may be used during determination of the phase relationship. The selective use of the opposite phase of the reference clock for the input of the delay line results in centralization of the lock point for most cases as well as improvement in the tuning range and the time to establish the initial lock, without requiring an additional delay line.

Abstract: A first PMOS transistor is connected between a supply terminal of a power supply voltage VCC and a connection node MON. A first NMOS transistor and a second NMOS transistor are connected between the connection node MON and ground. The first PMOS transistor and the first NMOS transistor are driven by an input signal. The second NMOS transistor is driven by a constant current IREF. In cooperation with the first NMOS transistor, the second NMOS transistor discharges the charge across a capacitor C1 connected to the connection node MON. A differential amplifier compares a potential at the connection node MON with a potential depending upon the constant current IREF, and outputs a result of the comparison.

Abstract: A programmable jitter signal generator is provided that includes a jitter distribution control unit, a selection unit in signal communication with the jitter distribution control unit, and a delay unit in signal communication with the selection unit; and a corresponding method of generating a programmable jitter signal includes programming a control unit, receiving a reference signal, delaying the received reference signal by a multiple of a base time increment, and selecting a delayed reference signal delayed by a desired multiple of the base time increment in accordance with the programmed control unit.

Abstract: This invention is about the direct conversion receiver. It is excellent the receiving sensitivity that DC off-set, matching characteristics of the relationship of I/Q circuits and noise characteristics are improved. In order to achieve this purpose, the direct conversion receiver uses vertical bipolar junction transistor available in standard triple-well CMOS technology in the switching element of mixer and base-band analog circuits. Furthermore, as using the passive mixer in the other practical example of this invention, this invention controls the occurrence of l/f noise. As using the vertical bipolar junction transistor available in standard triple-well CMOS in the base-band analog circuits, this invention realizes the direct conversion receiver that DC off-set, matching characteristics of the relationship of I/Q circuit and noise characteristics are improved.

Abstract: Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input clock signal is coupled through a series of first delay circuit for one-half the period of the input clock signal. A second series of feedback delay circuits mirror respective first delay circuits. After the input signal has been coupled through the first delay circuits, the mirrored signals from the first delay circuits are coupled through the feedback delay circuits. The delay of the feedback delay circuits is one-half the delay of the first delay circuits to provide a signal that is the quadrature of the clock signal.

Abstract: A timing domain crossing apparatus and method of transferring signals between timing domains are disclosed. A receiver samples a data signal with a sample clock in a first timing domain. The sampled data signal is expanded to a plurality of expansion signals, which are held valid for a plurality of consecutive active clock cycles. A data order adjuster may re-order the plurality of expansion signals to a predetermined order. A timing generator samples a command signal with an internal clock in a second timing domain to generate a re-timing strobe. The re-timing strobe may be temporally positioned to be within the expansion data window and used to sample the plurality of expansion signals in the second timing domain. The timing domain crossing apparatus and method of signal sampling may be incorporated in a semiconductor device, which may be fabricated on a semiconductor wafer and included in an electronic system.

Abstract: The invention provides a clock delay arrangement accounting for the worst-case delay situation of data signals, which is independent of the layout and technology. It comprises a main clock line; two dummy clock lines, each arranged parallel to the main clock line, and the main clock line disposed between the two dummy clock lines; and a clock source coupled to the main clock line and the two dummy clock lines, adapted to drive said dummy clock lines in phase opposition with respect to the main clock line.

Abstract: A lock detection circuit operatively associated with a phase-locked loop indicates when a feedback clock signal is locked to a reference clock signal. The lock detection circuit counts the number of rising and falling edges of the feedback clock signal that are detected between rising edges of the reference clock cycle. The lock detection circuit counts the number of consecutive valid cycles of the reference clock signal during which a single rising edge and a single falling edge of the feedback clock signal are detected. Lock detection circuit uses a state machine to assert a lock signal when the number of consecutive valid cycles counted exceeds a predetermined number. Where the lock detection circuit indicates locked signals and then detects a reference clock cycle that is not valid, the lock detection circuit continues to indicate lock if the next reference clock cycle is valid relative to a skewed feedback clock signal.

Abstract: A band-gap reference circuit for generation of voltages and currents independent of process, voltage, and temperature includes three inversely proportional to absolute temperature (IPTAT) current generators. The IPTAT current generators generate three currents that are added to generate a current independent of the absolute temperature. The generated current is passed through a switched capacitor resistor to generate the band-gap reference voltage across the switched capacitor resistor.

Abstract: An output clock is provided by a logic module and at least one flip-flop based on a reference clock. Each flip-flop receives the reference clock at a corresponding clock end and changes a signal level outputted at a corresponding output port according to rising or falling edges within each period of the reference clock. The logic module performs a logic operation among signals at each output port of the flip-flops to generate the output clock synchronized with the reference clock. Thereafter the output clock can be outputted through the data path provided by the logic module, and additional logical operations can be performed between the output clock and other signals.

Abstract: A data output circuit of a memory device comprises an output enable signal generating unit, an output driving unit, an output driving unit and an output enable control unit. The output enable signal generating unit generates a reference output enable signal in response to a read command and outputting a plurality of output enable signals in response to a rising DLL clock and a falling DLL clock. The output driving unit drives data synchronously with respect to the rising DLL clock and the falling DLL clock in response to the output enable signals at a read mode. The output enable control unit disables the falling DLL clock when the output enable signals are all disabled. As a result, current consumption is reduced because the falling DLL clock is generated only when the output enable signal is generated.

Abstract: An apparatus having a dual rail regulated reference loop. The reference loop includes a delay circuit powered by upper and lower supply voltages to generate a plurality of reference clock signals, and a voltage regulation circuit to adjust the upper and lower supply voltages according to a phase difference between a selected pair of the reference clock signals.

Abstract: A delay-locked loop (DLL) with feedback compensation is provided to increase the speed and accuracy of the DLL. After the variable delay line of the DLL is adjusted to minimize phase error, multiple clock cycles may be required before the adjusted signal is fed back to the phase detector. During this time, a signal replicating the adjusted signal is temporarily fed to the phase detector until the adjusted signal reaches the phase detector.

Abstract: A signal generating circuit includes a pulse generator generating a pulse responsive to a periodic clock reference signal. The pulse propagates through a plurality of series-connected delay elements in a measurement delay line. The measurement delay line is coupled to a series of latches that correspond to respective groups of delay elements in the measurement delay line. The delay element to which the pulse has propagated when the next pulse is received causes a corresponding latch to be set. The clock reference signal propagates through a signal generating delay line, which contains a sub-multiple of the number of delay elements in the measurement delay line, starting at a location corresponding to the set latch. The latch may remain set for a large number of periods of the clock reference signal so that it is not necessary for the clock reference signal to propagate through the measurement delay line each cycle.

Abstract: The invention provides an apparatus adapted for supplying a plurality of clock signals. The apparatus comprises a set of clock signal circuits for generating m clock signals of at least two different signal periods, with m being a natural number, and a superperiod signal-generating unit adapted for deriving, from a dedicated clock signal of said set of clock signals, a first superperiod signal. The signal period of said first superperiod signal is a common multiple of the clock signals' signal periods.

Abstract: In order to provide a semiconductor integrated circuit equipped with a clock distribution circuit that enables clock skew to be reduced without requiring great effort and without being affected by temperature variations or voltage variations, and a manufacturing method thereof, in a clock distribution circuit 1 installed in a semiconductor integrated circuit, part of the distribution path of a clock signal that passes from a first selector 11 of a first circuit block 10 that has many buffer stages via a first buffer stage 10A is used, and a distribution path of a clock signal to a second buffer stage 20A of a second circuit block 20 that has few buffer stages is constructed.