Abstract: A delay locked loop circuit with a first flip flop driven by a 0° clock and receiving the input data. A second flip flop by a 180° clock and receiving the input data. A first demultiplexer receives an output of the first flip flop and outputs peak data. A second demultiplexer receives an output of the second flip flop and outputs zero data. A timing recovery circuit outputs phase control bits based on the zero data and the peak data. A first phase interpolator outputs the 0° clock based on the phase control signal. A second phase interpolator outputs the 180° clock based on the phase control signal. A phase register receives the phase control signal from the timing recovery circuit. The first and second flip flops can be D flip flops. The first and second phase interpolators adjust relative phases of the 0° clock and 180° clock based on the phase control signal.

Abstract: A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the verniers being programmable to one of a plurality of timing steps within a delay range determined by a control signal applied to a bias input. A first and second control vernier is selected from the plurality of verniers, the first control vernier is programmed to a first delay, and the second control vernier is programmed to a second delay. The first and second control verniers are triggered together to generate respective first and second delay signals. A difference pulse signal is generated with a duty cycle corresponding to a difference between the generated first delay signal and second delay signal. The duty cycle of the pulse signal is compared to a duty cycle of the reference pulse signal to generate a difference signal pulse.

Abstract: A clock control circuit comprises a control circuit 102 for outputting a control signal for adding or subtracting a phase to a reference clock, which is an input clock or a clock generated from the input clock, on each clock period of the reference clock, and a phase adjustment circuit 101 fed with the input clock and outputting an output clock having the phase adjusted to the reference clock.

Abstract: A microwave filter is disposed on a substrate. The microwave filter is adapted for connecting a first microwave transmission line to a second microwave transmission line, configured such that a signal propagates from the first to second microwave transmission lines. The microwave filter encompasses a highpass component of filter disposed in a symmetrical configuration with respect to a median plane placed perpendicular to the surface of the substrate, including the central axis of the first and second microwave transmission lines; and a lowpass component of filter connected parallel with the highpass component of filter, the lowpass component of filter being disposed in a symmetrical configuration with respect to the median plane.

Abstract: The present invention provides a multi-stage delay clock generator including: a plurality of delay cells, each delay cell generating a delay signal to a subsequent delay cell in response to a delayed clock signal from a preceding delay cell and a delay control signal where a first delay cell among the plurality of delay cells receives an external clock signal, and each subsequent delay cell comprises a smaller delay step than the current delay cell; a phase detector, responsive to the external clock signal and a feedback clock signal, for generating a lock control signal; an integrator, responsive to the lock control signal, for generating the delay control signal; and a control unit for programming the delay cells.

Abstract: A dynamic phase adjustment circuit that includes a multi-tap delay line that receives a clock input signal. The multi-tap delay line includes an initial portion that is adjustable, and final portion after the adjustable portion. A number of registers receive the same data. However, the clock signal that causes the registers to sample is received from a corresponding delay element in the final portion of the multi-tap delay line. An edge detect and data decision circuit receives the sampled data values from each of the registers. Sampling resolution is improved over the PLL-based dynamic phase adjustment circuit since the clock signal is delayed using delay elements, which can be made with relatively small delays. Furthermore, the circuit does not contain excessive circuit elements thereby allowing the dynamic phase adjustment circuit to be contained in a small area.

Abstract: A phase detector in a delay locked loop circuit operates to determine the status of propagation of a first pulse of a reference clock signal (CKref) through a delay line (21). A first control signal (DOWN) is produced a in response to represent a first time at which the first pulse has progressed entirely through the delay line (21) and a later second time at which a next second pulse of the reference clock signal (CKref) arrives at a first input of the phase detector (24A). The delay of the delay line (21) is reduced in response to the first control signal (DOWN). A second control signal (UP) is produced in response to the status to represent a third time at which the second pulse of the reference clock signal (CKref) arrives at the first input of the phase detector (24A) and a later fourth time at which the first pulse of the reference clock signal (CKref) has progressed to the end of the delay line (21) and is used to increase the delay of the delay line (21).

Abstract: A method and apparatus for updating the control signal received by a delay chain in a DDR application. A register is used to regulate the control signal to the delay chain. The register only updates the signal at the delay chain when a signal is not passing through the delay chain. Additionally, the present invention is directed to a delay circuit that uses a plurality of PMOS and NMOS transistors connected in parallel to each other and to an inverter that provides the desired delay. The delay provided is achieved by sequentially turning off/on a series of the NMOS/PMOS transistor pairs.

Abstract: A section selection loop filter for use in a phase lock loop for reducing sizes of hardware and increase ranges of tuning, including a selection signal outputting part for setting a first to fourth sections according to an input tuning voltage, selecting a first to fourth selection signals corresponding to the first to fourth sensing sections respectively, and outputting the first to fourth selection signals to a filtering part, and a filtering part for receiving and filtering a charge-pumping signal from a charge pump based on the four selection signals for the four sensing sections.

Abstract: A timing circuit independently controls placement of the positive and negative edges of a periodic signal. This signal may then be used to control a wide variety of integrated circuit applications. The timing circuit includes separate programmable delay lines and a signal processor. Each delay line delays an input clock signal by a different increment of time. The signal processor then generates a timing signal from the clock signal, where the timing signal has a first edge controlled by the first delayed clock signal and a second edge controlled by the second delayed clock signal. The edges may be controlled so that the timing signal assumes different logical values for different amounts of time, thereby customizing the signal to any application. An example of one application includes using the timing signal control switching in a DC-DC converter.

Abstract: A semiconductor device includes a first circuit block which operates on a first power supply voltage to output a first digital signal having an amplitude equal to that of the first power supply voltage, a level shifting circuit into which the first digital signal is input and which converts the amplitude of the first digital signal to an amplitude equal to that of a second power supply voltage to output as a second digital signal via an output terminal, a second circuit block which operates on the second power supply voltage and into which the second digital signal is input, and a monitor circuit which produces a first signal to set the output terminal of the level shifting circuit to a predetermined potential in a case where the first power supply voltage drops below a predetermined voltage level.

Abstract: Provided is system for an improved programmable gain amplifier (PGA). The system includes an amplifier and a first gain control mechanism. The first gain control mechanism includes a circuit input port and is positioned along a feedback path of the amplifier. The first gain control mechanism is configured to (i) receive an input signal and (ii) moderate gains applied to the received input signal, the applied gains including gain values of greater than or equal to one. A second gain control mechanism is coupled to the first gain control mechanism and is integrated with a function of the amplifier. The second gain control mechanism (i) provides gain values of less than one and (ii) decreases a feedback factor of the amplifier when the gain values are provided having values of less than one.

Abstract: A low pass filter includes a differential amplifier including a positive input end, a negative input end, a positive output end, and a negative output end. A first resistive device is coupled between the negative input end and a first node. A second resistive device is coupled between the positive input end and the first node. A third resistive device substantially the same as the second resistive device is coupled between the negative input end and a second node. A fourth resistive device substantially the same as the first resistive device is coupled between the positive input end and the second node. A first capacitive device is coupled between the negative input end and the positive output end. Finally, a second capacitive device substantially the same as the first capacitive device is coupled between the positive input end and the negative output end.

Abstract: In a dual loop PLL having a frequency comparison loop and a phase comparison loop, when an input control circuit 30 of an up/down counter 8 receives an UP signal from a frequency comparator 7, the input control circuit 30 outputs a positive value of a ½ of a previous addition/subtraction result value. When the input control circuit 30 receives a DOWN signal from the frequency comparator 7, the input control circuit 30 outputs a negative value of a ½ of the previous addition/subtraction result value. A register 33 stores a count value. The adder 31 adds the output of the input control circuit 30 to the output of the register 33. Thus, the up/down counter 8 increments or decrements by a ½ value of the previous addition/subtraction result value, and the dual loop PLL performs a frequency comparison based on a dichotomizing search method. Therefore, even when the output frequency is high, the frequency comparison is efficiently performed, and the lock up time is reduced.

Abstract: A phase-lock loop (PLL) has an oscillator comprising a plurality of operating curves. A method for implementing a multi-transfer curve in a phase lock loop. A means of a finite state machine cooperating with a current cell, the unwanted loop gain is effectively reduced to produce a wide-ranging operating curve.

Abstract: A circuit having a process, voltage, and temperature (PVT) invariant delay element is disclosed. In one embodiment, the present invention includes a first and second operational transconductance amplifier (OTA), a first and second switched capacitor driven by a clock, and a first and second clock-controlled switch. In addition, the present invention includes a trip inverter, a delay inverter, and a plurality of transistors. In so coupling the first and second OTA, the first and second switched capacitor, the first and second clock-controlled switch, the trip inverter, the delay inverter, and the plurality of transistors, a circuit having a PVT invariant delay element is provided.

Abstract: A system or method for controlling a voltage controlled oscillator (VCO) or LO buffer includes an amplitude detector for detecting an amplitude value at a node corresponding to the at least one output line. A comparator compares the detected amplitude value with a predetermined amplitude value, and outputs a first digital value when the detected amplitude value is greater than the predetermined amplitude value, and a second digital value when the detected amplitude value is less than the predetermined amplitude value. An accumulator accumulates outputs of the comparator so as to provide an accumulated digital amplitude value. A digital-to-analog converter converts the accumulated digital amplitude value to an accumulated analog amplitude value. The analog accumulated amplitude value is provided as an updated bias control signal to the bias transistor of the VCO or LO buffer.

Abstract: In one embodiment, a pre-driver generates pre-driving signals based on control signals provided by a control circuit. The pre-driver has pre-driver power and ground connections. The pre-driving signals operate at a frequency band. A driver generates an output signal based on the pre-driving signals at an output pad. The output signal has a slew rate. The driver has driver power and ground connections. A low pass filter is coupled between the pre-driver and the driver power and ground connections to reduce the effect of noise at the pre-driving signals. The low pass filter has a cut-off frequency corresponding to the frequency of noise. In another embodiment, a plurality of pre-drivers generates pre-driving signals based on control signals provided by a control circuit. The pre-drivers have pre-driver power and ground connections. A plurality of drivers generates a plurality of output signals based on the pre-driving signals at output pads of an integrated circuit. Each of the output signals has a slew rate.

Abstract: A phase-locked loop circuit provides an output signal having a frequency depending on the frequency of a reference signal. The circuit includes a feedback circuit that derives a feedback signal from the output signal, a phase frequency detector that provides a control signal indicative of a phase difference between the reference signal and the feedback signal, a control circuit that controls the frequency of the output signal according to the control signal, and a conditioning circuit that conditions the control signal through a conditioning signal. The conditioning circuit includes a storage circuit that stores energy provided by the control signal and the conditioning signal during a first phase and transfers the accumulated energy to the control circuit during a second phase.

Abstract: A duty cycle correction circuit comprises an averaging circuit configured to receive a first signal and a second signal and provide a third signal, a duty restoration circuit configured to receive the third signal and a fourth signal and provide a fifth signal having a duty cycle closer to 50% than the first signal, and a synchronous mirror delay circuit configured to receive the fifth signal and provide the second signal.