Abstract: A charge pump generates a first sub up current and a second sub up current that vary complementarily with a change in a voltage at an output terminal. The charge pump also generates a first sub down current and a second sub down current that vary complementarily with the change in the voltage at the output terminal. With such complementary relationships, the total up/down currents remain substantially constant and balanced with the change in the voltage at the output terminal.

Abstract: A signal generating circuit includes a pulse generator generating a pulse responsive to a periodic clock reference signal. The pulse propagates through a plurality of series-connected delay elements in a measurement delay line. The measurement delay line is coupled to a series of latches that correspond to respective groups of delay elements in the measurement delay line. The delay element to which the pulse has propagated when the next pulse is received causes a corresponding latch to be set. The clock reference signal propagates through a signal generating delay line, which contains a sub-multiple of the number of delay elements in the measurement delay line, starting at a location corresponding to the set latch. The latch may remain set for a large number of periods of the clock reference signal so that it is not necessary for the clock reference signal to propagate through the measurement delay line each cycle.

Abstract: A delay-locked loop (DLL) with feedback compensation is provided to increase the speed and accuracy of the DLL. After the variable delay line of the DLL is adjusted to minimize phase error, multiple clock cycles may be required before the adjusted signal is fed back to the phase detector. During this time, a signal replicating the adjusted signal is temporarily fed to the phase detector until the adjusted signal reaches the phase detector.

Abstract: A loop filter of a compensating phase-locked loop contains capacitors formed from transistors with thin gate oxide dielectric layers. Leakage current leaks through the capacitors. To avoid jitter in the output signal of the phase-locked loop that would otherwise be caused by the leakage current, a leakage compensation circuit is provided. The leakage compensation circuit of a first embodiment replicates the leakage current using a replication capacitor and a current mirror. The voltage across the replication capacitor is proportional to the control voltage of a voltage-controlled oscillator of the compensating phase-locked loop. A second embodiment generates the compensation current by controlling the voltage on the gate of a transistor. The gate voltage depends on charge added and subtracted by a charge pump in addition to the charge pumps in the loop filter. A third embodiment applies a leakage compensation circuit to a delay locked loop.

Abstract: Clock generators capable of generating clocks with different frequency according to a binary code. A voltage controlled oscillation module generates a plurality of first clocks (D0˜Dm) with a first frequency (f0), in which the first clocks Di and Di-1 have a fixed phase difference and 1<i<m. A logic control circuit outputs a set of corresponding clocks arranged in a corresponding sequence according to the first clocks and a binary code. A clock synthesizer generates a second clock with a second frequency (f1) according to the set of corresponding clocks, in which f1=A/B f0, A<B and A and B are positive integers.

Abstract: An output signal is generated with a predetermined phase shift with respect to an input signal using a closed loop control. The input and output signal of the closed loop control are logically combined in accordance with first and second combinatory logic to generate first and second control signals. The first and second control signals selectively activate first and second current sources, respectively. The current supplied by the first current source charges a capacitance controlling the closed loop control, while the current supplied by the second current source discharges the capacitance. By selecting the types of the combinatory logics as well as the ratio of the currents supplied by the first and second current sources, the phase shift of the output signal with respect to the input signal can be variably adapted to individual requirements.

Abstract: A circuit is provided which is operable to program an electrically alterable element, e.g., fuse or antifuse, to a programmed state and determine whether the electrically alterable element is in the programmed state or not. Such circuit includes a multiple conduction state field effect transistor (“multi-state FET”) having at least one of a source or a drain coupled to the electrically alterable element to apply a current to the electrically alterable element. The multi-state FET has a first threshold voltage and a second threshold voltage, both being effective at the same time, the second threshold voltage being higher than the first threshold voltage.

Abstract: A clock generating circuit includes a first delay circuit array, which has a plurality of delay circuits, for measuring delay of an input signal, and a second delay circuit array for delay-replay having a plurality of delay circuits and being arranged in a direction opposite a direction of signal propagation in the first delay circuit array. On the basis of a signal that is output from a delay circuit at a position where a delay has been detected in the first delay circuit array, an output terminal of a delay circuit in the second delay circuit array that corresponds to the position where the delay has been detected in the first delay circuit array is fed back to an input terminal of this delay circuit to thereby construct a closed loop and form a ring oscillator circuit. An oscillation output signal of the ring oscillator circuit is extracted from an output terminal of the second delay circuit array.

Abstract: An integrated circuit driver includes an output stage having source drain paths of a PFET and NFET connected in series with each other across DC power supply terminals. A pair of inverters simultaneously responsive to a bilevel signal drive gate electrodes of the PFET and NFET. Each inverter includes a pair of switches and a resistor for connecting opposite polarity voltage sources to a separate capacitor connected in shunt with gate electrodes of the PFET and NFET. The inverters, resistors and capacitors prevent the PFET and NFET from being on simultaneously.

Abstract: A reference voltage signal (VpmpR), which is obtained by applying the output signal UPB/UP of a phase/frequency detection circuit (PFD) as a constantly locked state signal to a replica charge pump circuit (CPR) and then integrating, is compared in a correction voltage generation circuit (CMP) with a PLL circuit control voltage signal (Vpmp) for controlling a voltage-controlled oscillation circuit (VCO) by a desired voltage, this PLL circuit-controlled voltage signal being obtained by applying the output signal UPB/DN of the phase/frequency detection circuit as input to a charge pump circuit (CP) and then integrating, and the correction voltage signal (Vcmp) that is the result of the comparison then controls a charge pump bias circuit (CPBias) that controls the bias currents of the charge pump circuit and replica charge pump circuit.

Abstract: A PLL function may be implemented as a dual-loop structure having a first PLL circuit which generates an intermediate signal from the reference signal, and a second PLL circuit which generates an output signal from the intermediate signal. The intermediate signal frequency is preferably chosen at a value in which potential interference signals do not have much energy. The first loop preferably has low bandwidth to provide good input jitter attenuation, while second loop preferably has higher bandwidth to reduce phase noise of the output signal. The circuit preferably provides for a choice of several different intermediate frequencies to allow use where different intermediate frequencies may exist in each system. Moreover, in a system having two such dual-loop PLL circuits, each can be configured with a different intermediate frequency, so that interference from one to the other is reduced.

Abstract: A system for detecting the processing speed of an integrated circuit (IC) includes a flip-flop, a delay module, and a judge unit. The flip-flop receives a clock signal as a trigger signal and generates an inverted output signal. The delay module receives the inverted output signal, adjusts the delay time of the inverted output signal according to a selection signal, and outputs a delay signal to the flip-flop to have the flip-flop generate the output signal. The judge unit receives the output signal and generates a judge signal, which is enabled when the clock period of the output signal is longer than that of the clock signal.

Abstract: A circuit for generating a clock signal which is frequency aligned with a reference clock signal is disclosed. The circuit comprises a phase detector coupled to receive the reference clock signal and the generated clock signal. A frequency alignment circuit generates an average frequency alignment signal based upon comparison of the phase of a generated pulse train and the phase of a reference pulse train. Finally, an oscillator control circuit is selectively coupled to receive an output of the phase detector based upon the frequency alignment signal from the frequency alignment circuit. The oscillator control circuit generating an oscillator control signal for controlling the frequency of the generated clock signal. A method of generating a clock signal which is frequency aligned with a reference clock signal is also disclosed.

Abstract: A delay lock loop circuit for delaying a reference clock to lock a delayed clock. The delay lock loop circuit includes a clock divider for dividing a frequency of the reference clock by N to generate a frequency-divided clock, a programmable delay circuit electrically coupled to the clock divider for delaying the frequency-divided clock to generate the delayed clock, a 180° phase detector electrically coupled to the programmable delay circuit and the reference clock for detecting a phase change of the delayed clock, and a delay lock loop controller electrically coupled to the programmable delay circuit and the 180° phase detector for programming the programmable delay circuit to lock the delayed clock according to the phase change.

Abstract: A clock generation circuit receives a reference clock signal for outputting clock signals to peripheral circuits. A duty ratio of at least one of output buffer signals output from buffer circuits included in the clock generation circuit is varied so that a duty ratio of at least one of the clock signals can be varied.

Abstract: A delay-locked loop (DLL) acquires correct lock when the delay line on the DLL delays a reference signal by one clock period. False lock occurs when the delay line delays the reference signal by more than one clock period. False lock may be detected by a false lock detector. The false lock detector may include (1) flip-flops to take samples of the delay line outputs and (2) combinational logic for detecting patterns in the samples that may indicate false lock. Once false lock has been detected, a hold circuit may ensure that false lock persists for at least the amount of time required by the DLL to acquire lock (i.e., to prevent reset of the DLL before it has acquired lock). After this determination is made, a reset generator may produce a reset signal for resetting the DLL.

Abstract: An output stage interface circuit (1) comprises a main bipolar transistor (Q1) coupling a data output terminal (5) to a first rail (2) to which the positive of the power supply voltage (VDD) is applied, and a substrate diffusion isolated main NMOS transistor (MN1) coupling the data output terminal (5) to a second rail (3) which is held at ground. Control signals from a data control circuit (6) selectively operate the main bipolar transistor (Q1) and the main MOS transistor (MN1) for determining the logic high and low states of the data output terminal (5) during data output.

Abstract: A semiconductor device includes a memory and a power voltage interrupter configured to interrupt an external power voltage applied to circuitry of the semiconductor device responsive to a Deep Power Down (DPD) command signal generated in a DPD mode of the memory. A power voltage shifter is configured to shift a power voltage in the circuitry to a specific level responsive to the DPD command signal.

Abstract: A circuit for generating stable signal edges includes an output driver circuit having a current path for varying a charge on a capacitor in response to an input signal and constant current generation circuitry for maintaining a constant current through the current path of the output driver circuit and varying the charge on the capacitor to produce an output signal with a stable edge.

Abstract: PLL circuits are provided in which a voltage-controlled oscillator (VCO) comprising one or more voltage-controlled delay units (VCDs) is initialized with the control voltage of a voltage-controlled delay line (VCDL) having substantially identical VCDs. In general, VCDLs provide for faster signal locking than do VCOs. The VCO locks to a frequency of a reference signal at substantially the same time that the VCDL locks to the reference signal. Lock time of the PLL circuit is thereby reduced. A timing circuit prevents the VCO control voltage from being adjusted during phase locking of the VCO. This allows the VCO frequency lock to be maintained during the VCO phase locking. Lock time is thereby further reduced. The timing circuit locks the VCO to a phase of the reference signal by restarting oscillation of the VCO at an appropriate time.