Abstract: A waveform output device includes a data reception unit which receives at least a part of a waveform pattern generation program transmitted from an external device connected to the data reception unit through a data line, the waveform pattern generation program being able to generate output data information and output time information, a tentative storage device which tentatively stores the waveform pattern generation program received from the data reception unit, a data processing unit which processes the waveform pattern generation program in the tentative storage device to generate the output data information and the output time information, and an output waveform generation unit which outputs waveform data to drive an electronic device based on the output data information and the output time information.

Abstract: Matched current delay cells and a delay locked loop based on such cells that may be used for timing data interfaces between semiconductor devices is described. In one embodiment, the delay cell includes a delay cell having a PMOS portion and a NMOS portion, gates of the PMOS portion being coupled to a vp-bias and gates of the NMOS portion being coupled to a vn-bias, the delay cell further being coupled to a reference clock to drive a pulse output of the delay cell, a first bias generation circuit to generate the vn-bias based on a phase comparison of the pulse output to the reference clock, and a second bias generation circuit to generate the vp-bias based on a reference voltage and the vn-bias.

Abstract: An amplifier circuit having an output delay that is selectively changed in accordance with a common mode voltage level. A replica delay circuit adapted for use within an internal clock generator include such an amplifier circuit. The amplifier circuit includes a first amplifier generating internal signal in response to input signals changes a common mode voltage level of the internal signals in response to control signals. The amplifier also includes a second amplifier comparing voltage levels of the internal signals, generating an output signal in accordance with a comparison result, and changing a duty cycle of the output signal when the common mode voltage level of the internal signals is changed.

Abstract: A delay locked loop including a first circuit and a second circuit. The first circuit is configured to receive a clock signal having a frequency and to lock onto the clock signal and provide a first locked clock signal over a first frequency range and a second locked clock signal over a second frequency range. The second circuit is configured to signal the first circuit to lock onto the clock signal to provide the second locked clock signal as the frequency changes from the first frequency range to the second frequency range. Also, the second circuit is configured to signal the first circuit to provide a locked one of the first locked clock signal and the second locked clock signal in a locked output clock signal.

Abstract: A power-on reset circuit and method for the same may provide reset signals during power-up and/or power-down cycles, to reduce the chances of error. An error may occur, for example, due to voltage fluctuations and/or the ambient temperature of circuit components. Reducing the chances of error during a power-up cycle may include setting an output node of a circuit to a reset state when a power supply voltage reaches a first voltage level and outputting a power-on reset signal to the output node when the power supply voltage equals a second voltage level higher than the first. Reducing the chances of error during a power-down cycle may include setting the output node to a reset state when the output node reaches a third voltage level between the first and second voltage levels.

Abstract: A bias circuit, which generates a bias voltage, has a first MOS transistor coupled between a first reference voltage terminal and a voltage dividing node and a second MOS transistor coupled in parallel with the first MOS transistor. The first MOS transistor may have a first ON-state resistance, and the second MOS transistor may have a second ON-state resistance which is lower than the first ON-state resistance. Furthermore, the bias circuit has a resistance circuit coupled between the voltage dividing node and a second reference voltage terminal and a voltage generator coupled with the first node. The voltage generator outputs the bias voltage in dependence upon an electrical potential on the voltage dividing node.

Abstract: A duty cycle correction circuit for use in a semiconductor device, which synchronizes with an external clock and corrects a duty cycle, is provided. The duty cycle correction circuit includes a modulator of an inverter structure having at least one or more transistors. The modulator receives a control signal through a source terminal and a bulk of any one of the transistors and corrects a duty cycle in response to an external clock signal. The duty cycle correction circuit also includes a driver that converts an output signal of the modulator into a full swing level and outputs the converted output signal of the modulator, and a feedback loop that generates the control signal in response to an output signal of the driver.

Abstract: A system is provided that includes a phase lock loop component to output a first signal based on a reference clock signal and a feedback clock signal. A clock distribution network may distribute a clock signal based on the first signal output from the phase lock loop component. Additionally, a delay lock loop component may deskew a signal and adjust the clock signal distributed by the clock distribution network.

Abstract: A PUR circuit for generating a reset signal includes a first node for receiving a reference voltage and a second node for receiving a supply voltage that is referenced with respect to the reference voltage. The circuit further includes a voltage level detector coupled between the first node and a third node, the voltage level detector being configured to generate a first control signal at the third node. The voltage level detector includes a first transistor having a first threshold voltage associated therewith. A resistance element is coupled between the second node and the third node, the resistance element having a first resistance value associated therewith. The circuit also includes an inverter having an input coupled to the third node and having an output for generating a second control signal in response to the first control signal. The inverter includes a second transistor having a second threshold voltage associated therewith which is lower than the first threshold voltage.

Abstract: A dual-edge synchronized sampler having an efficient implementation for high speed and high performance operation is described. The sampler receives a data input signal and a clock input signal and uses an asynchronous level mode state machine to sample the data input signal responsive to level changes in the clock input signal. In some embodiments, the sampler includes at least one differential logic block for implementing the asynchronous level mode state machine. The sampler has symmetric clock-to-Q propagation delays for both rising and falling edges of the clock input signal. The sampler may include toggle functionality, and may include edge control logic for configuring the sampler as one of a rising edge and falling edge sampler.

Abstract: A voltage controlled delay loop and method are disclosed for clock and data recovery applications. The voltage controlled delay loop generates clock signals having similar frequency and different phases. The voltage controlled delay loop comprises at least one delay element to generate at least two phases of a reference clock; a central interpolator for interpolating the at least two phases of the reference clock to generate an interpolated signal; and an input that injects the interpolated signal into a delay stage. The central interpolator provides a fine phase control. In addition, a coarse phase control can optionally be achieved by selectively injecting the interpolated signal into a given delay stage. A further voltage controlled delay loop is disclosed with coarse and fine phase control using a number of interpolators.

Abstract: A clock frequency divider is provided which has first through Pth (where P is an integer) sub-counters, each capable of counting M+1 clock pulses and provided in parallel, and first through Pth clock signals are provided to the sub-counters, which has same period as a reference clock signal and are sequentially shifted by 1/P of the period of the reference clock signal. Of the first through Pth sub-counters, when the Nth sub-counter (where N is an arbitrary number from 1 to P) finishes counting a prescribed number M of reference clock pulses, all the other sub-counters are initialized, or, at least the (N+1)th sub-counter is initialized.

Abstract: A method and circuit configuration for synchronous resetting of an multiple clock domain circuit such as an Application Specific Integrated Circuit (ASIC) combine an asynchronous reset signal with a functional signal using a clocked reset tree of synchronous logic elements.

Abstract: An apparatus and a method of controlling clock phase alignment with a dual loop of a hybrid phase and time domain for clock source synchronization in electronic devices are described. The coarse calibration unit generates a plurality of output signals, the output signals having a plurality of phase intervals therebetween. A predetermined phase angle is divided by the number of the output signals to generate one of the phase intervals. The first fine calibration unit connected to the coarse calibration unit delays the output signals generated from the coarse calibration unit by coupling a programmable delay circuit to adjust the phase of a feedback signal toward the phase of a reference signal. The phase detector connected to the first fine calibration unit is used to detect a phase difference between the reference and the feedback signal and outputting an indicating signal corresponding to the phase difference between the reference and the feedback signal.

Abstract: Provided are a duty cycle correction circuit and method for duty cycle correction in a delay locked loop using an inversion locking scheme.

Abstract: An integrated circuit for generating a clock signal includes a voltage conversion unit, a maximum power determination unit, a clock control unit and a clock generator. The voltage conversion unit converts an external power supply voltage into an internal power supply voltage and detects a variance in current consumption of a functional block to generate a detected voltage, wherein the functional block consumes a predetermined current using the internal power supply voltage. The maximum power determination unit determines a maximum current consumption of the functional block and converts the maximum current consumption to a corresponding maximum allowed voltage. The clock control unit generates at least one frequency control signal based on a comparison between the detected voltage and the maximum allowed voltage. The clock generator generates the clock signal whose frequency is adjusted according to the frequency control signal.

Abstract: In the proposed method of generating a pulsed output signal from a periodic ramp signal and a reference voltage, the linear range of duty cycles of the pulsed output signal is significantly extended to minimum values. The ramp signal and the reference voltage are applied to inputs of a comparator and the output signal is taken from an output of the comparator. The ramp signal has a ramp that extends between a minimum voltage level and a maximum voltage level. The duty cycle of the pulse signal is controlled by varying the reference voltage between the minimum and maximum voltage levels. The ramp has an initial start section extending from the minimum voltage level and a main section extending between the initial section and the maximum voltage level. The ramp slope has a constant value over the main ramp section and a value greater than the constant value over the initial section.

Abstract: An apparatus for synchronizing a clock using a source synchronous clock is disclosed. The apparatus includes: channel receivers for receiving a source synchronous channel; divider for dividing the source synchronous clock to a low frequency clock; selectors for selecting one of the divided source synchronous clock and a system clock as a reference clock; detectors for generating a phase difference signal; phase difference signal selectors for selecting a phase difference signal from the detectors and a phase difference signal from an internal logic; and voltage oscillators for transmitting a clock synchronized to a source synchronous channel to the external optical transmission system by generating a predetermined synchronous frequency according to the selected phase difference signal.

Abstract: A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.

Abstract: A loss-of-signal (LOS) detector includes a variable gain amplifier with an input receiving an input signal, a threshold comparator with a first input receiving a signal derived from an output of the variable gain amplifier, a second input receiving a reference level and an output providing a loss-of-signal indication signal. The variable gain amplifier has a gain control input receiving a gain control signal derived from the output of the threshold comparator and such that the gain of the variable gain amplifier is set to a lower value when the loss-of-signal indication signal is active, and set to a higher value when the loss-of-signal indication signal is not active. Accordingly, the LOS detector needs only one decision level for both of the LOS and NotLOS decisions, which is set in the linear range of the signal detector so that the hysteresis is reproduced precisely.