Abstract: A programmable high-speed frequency divider is provided in which a stage for forming a frequency divider, which is capable of being programmed with a programmable dividing ratio, is simplified in order to reduce the area and circuit complexity. The programmable frequency divider includes a first synchronizing element coupled to an output of a logic detection circuit for generating a synchronized divider output, an additional synchronizing element coupled to the output of the logic detection circuit for receiving its clock from the output of a divide-by-two circuit and generating a special synchronized load output, and combinational logic blocks that receive the load output and generate load signals for bit-cells for detecting the state of all stages. Preferably, start-up circuitry is included within the frequency divider to ensure that the frequency-divider never goes into a false state.

Abstract: A flip-flop circuit includes a differential stage coupled to a latch stage. The differential stage comprises cross-coupled dynamic logic and only provides a single output to the latch stage. During an evaluation phase, the state of a data input signal is sensed. Depending upon the state of the data input signal, either an output side or reference side of the differential stage is discharged. Also, during the evaluation phase, the latch stage write port is enabled while feedback is disabled, and the flip flop thereby samples and stores an output signal from the output side of the differential stage. Upon initiation of the next precharge phase, the latch stage write port is disabled and feedback is enabled, thereby retaining its present state. Only a single side of the differential stage is used to drive the latch stage and the differential stage may be implemented in an asymmetric fashion.

Abstract: A frequency divider circuit is disclosed with at least one push-pull divider with adjustable division ratio and a connected converter device. The circuit converts a clock signal delivered by a push-pull divider into a single-ended signal. A first and a second single-ended divider are connected to the output of the converter device, and a feedback path is provided, which is connected to the output of the push-pull divider and to the outputs of the first and of the at least one second single-ended divider, and which includes an evaluation circuit. This circuit has first and second inputs which are connected to the first and second single-ended dividers in such a way that a future state of the clock signal delivered by the single-ended divider in question can be supplied to the inputs of the evaluation circuit. The evaluation circuit evaluates states of the clock signals delivered by the first and second single-ended dividers, i.e.

Abstract: Embodiments may include a duty cycle controller to adjust the duty cycle of the clock signal based upon a delay signal and an input clock signal. A duty cycle detector may determine signals with frequencies based upon the duty cycle of the output signal and a correction module may compare the frequencies of the detector signals to generate the delay signal. In some embodiments, once the duty cycle of the output clock signal reaches the desired duty cycle such as fifty percent, the correction module may be turned off.

Abstract: A circuit for timing adjustment includes a PLL circuit configured to generate a phase-adjusted clock signal in response to phase comparison between an input clock signal and a delayed clock signal, a feedback path configured to delay the phase-adjusted clock signal for provision as the delayed clock signal to the PLL circuit, a first timing correction circuit configured to add a predetermined delay time to the feedback path, an output data circuit configured to supply output data at first timing responsive to the phase-adjusted clock signal, a second timing correction circuit configured to delay the first timing by the predetermined delay time to generate second timing different from the first timing, and an input data circuit configured to latch input data at the second timing.

Abstract: A latch type sense amplifier includes a latch unit, an amplifying unit and a circuit module for charging or discharging the latch unit. The latch unit is configured by two sets of serially coupled PMOS and NMOS transistors, whose gates and drains are cross-coupled. The amplifying unit is coupled between the latch unit and a complementary power supply for controlling the latch unit in response to a bit line signal and a complementary bit line signal. The circuit module is designed to charge or discharge the data storage node and the complementary data storage node of the latch unit in response to the bit line signal and the complementary bit line signal, without using a current path across the NMOS transistors therein, such that the data storage node and the complementary data storage node are charged or discharged in a manner insensitive to a mismatch between the two NMOS transistors.

Abstract: Embodiments of the present invention include circuits and methods for dividing high frequency signals. In one embodiment the present invention includes a divider circuit comprising a differential circuit having first and second inputs to receive a first differential signal, a first frequency control input and first and second differential outputs, wherein the differential circuit has a first bias current. The divider circuit further includes a cross-coupled circuit having outputs coupled to the differential circuit outputs and a second frequency control input, wherein the cross-coupled circuit has a second bias current. Embodiments of the present invention may include circuits for controlling the relationship between bias currents and circuit parameters that vary with process or temperature or both.

Abstract: A delay locked loop (DLL) includes a delay unit configured to delay an input clock signal by a specified amount to produce a delayed clock signal. A phase detector receives as input the input clock signal and the delayed clock signal and outputs a signal proportional to the phase difference between the input clock signal and the delayed clock signal to provide a control voltage for adjusting the delay to the specified amount. A pulse swallower removes a pulse from the input clock signal or from the delayed clock signal to reverse the direction of the control signal.

Abstract: A delay-locked loop (DLL) circuit comprises a voltage controlled delay line (VCDL) including a plurality of identical delay stages connected in series, and a feedback loop including a phase comparator for controlling the VCDL such that the total delay over a number of stages matches the period of the periodic reference signal. Signal outputs are connected to derive their respective output signals from respective nodes within the delay line. The phase comparator compares the phase of first and second differently delayed versions of the reference signal from respective nodes within the variable delay line separated only by a plurality of identical delay stages.

Abstract: Circuits and methods for aligning two or more signals including a first and second signal. In one embodiment, a shift register generates two or more shifted copies of the second signal, and each of a plurality of phase detectors receives the first signal and one of the shifted copies of the second signal, each phase detector providing an output indicating whether the first signal is substantially aligned with the shifted copy of the second signal. A multiplexer may also be provided for receiving each of the shifted copies of the second signal, the multiplexer having a plurality of select lines coupled with the output signals of the phase detectors. Some embodiments may include a power saving mode.

Abstract: An output buffer with an improved slew rate and method thereof. The output buffer may include a differential amplifier, a controller and an output unit. The output buffer may generate a pull signal and a control signal based on received input and output signals. The controller may transition an output node to a control voltage in response to the control signal and a bias voltage. The output unit may maintain the first output signal between a given voltage and the control voltage based on the pull signal and the bias voltage.

Abstract: A device such as a programmable logic device (“PLD”) includes circuitry for detecting the PPM frequency difference between two input clock signals. For example, this circuitry may accept a user-programmable PPM threshold value and output a signal when this threshold value is met.

Abstract: A timing delay generator for supplying a signal delayed by a predetermined period comprises a vernier that provides variable delays for a main signal, the delays being sensitive to temperature variation, a sensor for sensing the vernier's temperature and a feedback loop to maintain the temperature of the silicon die at a constant level and thus, to provide the high long-term accuracy of the timing delay generator.

Abstract: A loop filter includes a first resistor, a first capacitor, and an amplifier with a specific gain. Wherein, the amplifier includes an input terminal coupled to an input terminal and an output terminal of the loop filter through the first resistor. In addition, the amplifier also includes an output terminal coupled to the input terminal of the amplifier through the first capacitor.

Abstract: Without shortening clock pulse duration serving as a unit time of a pulse generator, a pulse-width control is possible in which pulse duration varies in increments of a time length shorter than the unit time. A time width Ton_s of a pulse width finely dividing signal Vs from a DSP 17 varies by clock pulse duration Tclk in response to variations in an output voltage Vo. A time control circuit 18 that has received the pulse width finely dividing signal Vs generates, in a control signal Vd, varying segments 30, 31 for making the time width of the pulse drive signal Vg vary by a shorter time ?Td than the clock pulse duration Tclk. Consequently, resolution of the time width of the pulse drive signal Vg is improved so as to be higher than the clock pulse duration Tclk, which is time resolution of the DSP 17 itself.

Abstract: A DLL-based programmable clock generator using a threshold-trigger delay element and an edge combiner is proposed. A threshold-trigger delay element with full swing complementary output signals consumes no dc power. It exhibits small delay error resulting reduced out jitter. It also increases the linearity of delay time versus control voltage. The circular edge combiner can multiply the input signal at a lower supply voltage. The rise and fall time of output signal are more symmetrical. It also present the multiplication factor of the clock generator can be easy to choose with the increasing of the number of delay elements.

Abstract: A delay circuit comprises: N-stage circuits having a first circit to a N-th circuit connected in cascade, the input signal being input to the first circuit and a transmission signal delayed by a (k-1)-stage (where 2?k?N) circuit is input to a k-th circuit for sequential transmission; a common delay circuit for delaying the transmission signal of each stage commonly; and path control means for controlling a path of an i-th (1?i?N) circuit so that during a predetermined period from an edge timing of a signal input to the i-th circuit to an edge timing of the transmission signal delayed by the common delay circuit through the i-th circuit, the common delay circuit is connected to a signal path, and during the other period, the common delay circuit is disconnected from the signal path, wherein the delayed signal passing through the common delay circuit N times is generated.

Abstract: Disclosed is an apparatus for multiple-divisor prescaler, which includes an odd/even core divider, a divisor control logic unit, an odd number inserted mechanism, and an n-order divided-by-2 divider with changeable trigger edges. This invention uses a clock toggle mechanism to vary the trigger edges of each divided-by-2 divider in the n-order divider, and associates the odd/even core divider to realize the multiple-divisor prescaler apparatus. Thereby, it achieves the purpose of being divided by 30/31. In addition, it increases the divisor range up to 2n?1+2 and 2n+1 through the use of the clock toggle mechanism.

Abstract: A rotational frequency detector system including a rotational frequency detector responsive to a data signal and a clock signal. The rotational frequency detector is configured to compare the frequency of the clock signal to the frequency of the data signal to define frequency up and frequency down signals that adjust the frequency of the clock signal to be equal to the frequency of the data signal. A step control system is responsive to the rotational frequency detector and a step clock signal and is configured to define predetermined pulse widths for the frequency up and frequency down signals.

Abstract: Enclosed is a duty cycle correction device for correcting a duty cycle of a clock signal output from a delay locked loop (DLL) device by using a phase mixer. The duty cycle correction device comprises: a mixer for receiving a first clock signal and a second clock signal and outputting a first signal; a phase splitter for receiving the first signal and outputting a third clock signal by delaying the first signal and a fourth clock signal by delaying and inverting the first signal; a duty detection unit for receiving the third and fourth clock signals and detecting a difference between their duty cycles; a combination unit for outputting a second signal; and a shift register for outputting a control signal to adjust a mixing ratio of the first and second clock signals in response to the second signal.