Patents Examined by Long Le
  • Patent number: 9650242
    Abstract: An electromechanical device comprises a substrate structure, a set of electrodes, one or more anchor trenches, and one or more multi-faced components. For example, each of the one or more multi-faced components comprises an isolation region formed on a first portion of the surface of the component, a high resistance region formed on a second portion of the surface of the component, and a low resistance region formed on a third portion of the surface of the component. For example, the synapse device is configured to provide an analog resistive output, ranging between the high resistance region and the low resistance region, from at least one of the set of electrodes in response to a pulsed voltage input to at least another one of the set of electrodes.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: May 16, 2017
    Assignee: International Business Machines Corporation
    Inventors: Qing Cao, Kangguo Cheng, Zhengwen Li, Fei Liu
  • Patent number: 9627036
    Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: April 18, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tan-Ya Yin, Ming-Jui Chen, Chia-Wei Huang, Yu-Cheng Tung, Chin-Sheng Yang
  • Patent number: 9607907
    Abstract: A picking-up and placement process for electronic devices comprising: (a) providing a first substrate having a plurality of electronic devices formed thereon, the electronic devices being arranged in an array, and each of the electronic devices comprising a magnetic portion; (b) selectively picking-up parts of the electronic devices from the first substrate via a magnetic force generated from an electric-programmable magnetic module; and (c) bonding the parts of the electronic devices picked-up by the electric-programmable magnetic module with a second substrate.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: March 28, 2017
    Assignees: Industrial Technology Research Institute, PlayNitride Inc.
    Inventors: Ming-Hsien Wu, Yen-Hsiang Fang, Chia-Hsin Chao
  • Patent number: 9595646
    Abstract: According to one embodiment, an electronic component includes a metal portion, a mold resin covering at least a part of the metal portion, and a molecular adhesion layer provided between a surface of the metal portion and the mold resin.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: March 14, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akihiko Happoya, Daigo Suzuki
  • Patent number: 9590047
    Abstract: A method of manufacturing a silicon carbide (SiC) bipolar junction transistor (BJT) and a SiC BJT (100) are provided. The SiC BJT comprises an emitter region (150), a base region (140) and a collector region (120). The collector region is arranged on a substrate (110) having an off-axis orientation of about 8 degrees or lower. A defect termination layer (DTL, 130) for terminating dislocations originating from the substrate is arranged between the substrate and the collector region. The collector region includes a zone (125) in which the life time of the minority charge carriers is shorter than in the base region. The present invention is advantageous in terms of improved stability of the SiC BJTs.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: March 7, 2017
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventor: Martin Domeij
  • Patent number: 9583538
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnects extending in a first direction, a plurality of second interconnects extending in a second direction, a plurality of stacked films respectively provided between the first interconnects and the second interconnects, each of the plurality of stacked films including a variable resistance film, a first inter-layer insulating film provided in a first region between the stacked films, and a second inter-layer insulating film provided in a second region having a wider width than the first region. The second inter-layer insulating film includes a plurality of protrusions configured to support one portion of the plurality of second interconnects on the second region. A protruding length of the protrusions is less than a stacking height of the stacked films.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: February 28, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kotaro Noda
  • Patent number: 9564598
    Abstract: An organic light-emitting device includes an anode, a cathode, and an organic layer between the anode and the cathode, wherein the organic layer includes a mixed organic layer, and the mixed organic layer includes at least two different compounds, and a triplet energy of at least one compound of the at least two different compounds is 2.2 eV or higher. The organic light-emitting device according to embodiments of the present invention may have a low driving voltage, a high efficiency, and a long lifespan.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: February 7, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Naoyuki Ito, Seul-Ong Kim, Youn-Sun Kim, Dong-Woo Shin, Jung-Sub Lee
  • Patent number: 9564332
    Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a metal gate stack formed over the semiconductor substrate. The semiconductor device also includes an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the metal gate stack includes a metal gate electrode. The semiconductor device further includes a metal oxide structure formed over the insulating layer and in direct contact with the insulating layer. The metal oxide structure includes an oxidized material of the metal gate electrode.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: February 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Jia Hsieh, Chih-Lin Wang, Chia-Der Chang
  • Patent number: 9493702
    Abstract: Provided is a garnet-based phosphor doped with thorium and a light emitting device using the same. In particular, a garnet-based phosphor having superior light characteristics and heat stability by using thorium as an activator, when compared to a conventional garnet phosphor using cerium as an activator, and a light emitting device using the same as a light source are provided.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: November 15, 2016
    Assignee: FORCE4 CORP.
    Inventors: Ho Shin Yoon, Seung Hyok Park, Jun Cho, Hye Min Boo, Sung Kyoung Jung
  • Patent number: 9450034
    Abstract: A display device includes a substrate including a display region and a peripheral region, display structures at the display region of the substrate, a plurality of blocking structures at the peripheral region of the substrate wherein the blocking structures have heights different from each other, an organic layer on the display structures and the blocking structures, and an inorganic layer on the organic layer.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: September 20, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sun-Youl Lee, Yeon-Heok You, Sang-Won Seo, Jung-Ju Yu
  • Patent number: 9449548
    Abstract: An organic light emitting display device for displaying 2D and 3D image, the organic light emitting display device including a scan driver for supplying a scan signal to a plurality of scan lines; a data driver for supplying a data signal to a plurality of data lines; a plurality of pixels that located at crossing regions of the scan lines and the data lines for controlling a current flowing from a first power driver to a second power driver via an organic light emitting diode; a data processor for classifying data supplied from outside as 2D or 3D data, and for producing 2D or 3D; and a timing controller for transmitting 2D or 3D data supplied from the data processor to the data driver, wherein the timing controller is configured to set the pixels in a non-emission state during a scan period.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: September 20, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventor: Kwang-Sub Shin
  • Patent number: 9431584
    Abstract: Light emitting systems are described. Particularly, light emitting systems and light converting components utilized within these systems are described. The light emitting system and components are formed such that dark-line defects do not interfere with the light emitting system efficiency.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: August 30, 2016
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Michael A. Haase, Thomas J. Miller, Terry L. Smith, Xiaoguang Sun, Junqing Xie
  • Patent number: 9426359
    Abstract: Provided is a digital image signal processing method, a recording medium for recording the method, and a digital image signal processing apparatus, in which a storage area of a memory may be efficiently used and an image desired by a user can be stored even when the storage area of the memory is insufficient. According to the present invention, a scene of an image may be recognized and a resolution and an image quality may be modified according to the recognized scene, thereby efficiently using the storage area of the memory.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: August 23, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jang-won Lee
  • Patent number: 9418910
    Abstract: A circuit pattern is bonded to a top surface of a ceramic substrate. A cooling body is bonded to an undersurface of the ceramic substrate. An IGBT and a FWD are provided on the circuit pattern. A coating film covers a junction between the ceramic substrate and the circuit pattern, and a junction between the ceramic substrate and the cooling body. A mold resin seals the ceramic substrate, the circuit pattern, the IGBT, the FWD, the cooling body, and the coating film etc. The ceramic substrate has higher thermal conductivity than the coating film. The coating film has lower hardness than the mold resin and alleviates stress applied from the mold resin to the ceramic substrate. The circuit pattern and the cooling body includes a groove contacting the mold resin without being covered with the coating film.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: August 16, 2016
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Noboru Miyamoto, Naoki Yoshimatsu
  • Patent number: 9418998
    Abstract: Semiconductor devices are provided. A semiconductor device includes a bit line structure and a contact plug. The contact plug is adjacent a sidewall of the bit line structure and is on a sloped surface of the bit line structure. Moreover, in some embodiments, a level of the sloped surface of the bit line structure becomes lower as the sloped surface approaches the sidewall of the bit line structure.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: August 16, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Eun Kim, Hoon Jeong, Jae-Hyun Kim, Dong-Won Lee, Jung-Gu Han, Ji-Hye Hwang
  • Patent number: 9412881
    Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: August 9, 2016
    Assignee: Silanna Asia Pte Ltd
    Inventors: Jacek Korec, Boyi Yang
  • Patent number: 9404762
    Abstract: A navigation apparatus includes: a current-position information acquisition section obtaining measured current-position information; a camera section obtaining a captured image of a subject; a direction detection section detecting a direction when obtaining the captured image by the camera section; from characteristic-point information related to multiple predetermined characteristic points stored in a storage section, a characteristic-point information extraction section extracting the characteristic-point information related to the characteristic points located in the vicinity of the current position and in a range shown in the direction; and a control section displaying the captured image on a display section, wherein the control section displays a predetermined direction line indicating a distance from the current position on the captured image, obtains a distance and a direction from the current position to the characteristic point, and displays the characteristic-point information at a position correspo
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: August 2, 2016
    Assignee: Sony Corporation
    Inventor: Hiromasa Miyata
  • Patent number: 9380697
    Abstract: An electronic device includes: electronic elements; expandable and contractible conductors each disposed between two of the electronic elements adjacent to each other; a seal which covers the electronic elements and the conductors except principal surfaces of the electronic elements and first surfaces of the conductors, the principal surfaces of the electronic elements and the first surfaces of the conductors being present on a same plane on which surfaces of the seal are present; and leading electrode films each of which is attached in a film-like form to three surfaces which are the surface of the seal positioned between one of the electronic elements and one of the conductors, the first surface of the conductor, and part of the principal surface of the electronic element, to electrically connect the electronic element and the conductor through the leading electrode film.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: June 28, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Yoshihiro Tomita, Mitsuhiro Kasahara
  • Patent number: 9367315
    Abstract: Provided is an image processing device capable of an image processing with using a general-purpose image processing hardware in accordance with video input without mediation of a CPU. The image processing device includes: a storage medium for storing an image data acquired by video inputting unit for acquiring video images; a CPU for a general processing; image processing unit for processing the image data stored in the storage medium; setting unit for determining a processing content of the image processing unit; a command list indicating an order of setting and activating the image processing unit; and command writing unit for setting and activating the image processing unit based on the command list in synchronization with input of the image data from the video inputting unit without mediation of the CPU.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: June 14, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Hideaki Kido, Shoji Muramatsu, Hiroyuki Hamasaki, Akihiro Yamamoto
  • Patent number: 9362421
    Abstract: In a semiconductor device, a support wall is formed between storage nodes to more effectively prevent leaning of a capacitor, and the storage nodes are formed using a damascene process, which may increase a contact area between each storage node and a storage node contact.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: June 7, 2016
    Assignee: SK HYNIX INC.
    Inventors: Cheol Hwan Park, Dong Sauk Kim