Patents Examined by Long Le
  • Patent number: 9357231
    Abstract: In a system for visualizing a stereoscopic image by displaying separate video images for the left and right eyes, sub-picture data (GRD) is created for the left eye and displayed superimposed on left-eye video data (VDD) as a left-eye sub-picture without change. The right-eye sub-picture (106) is displayed by shifting the horizontal positions at which the sub-picture data created for the left eye is displayed by prescribed widths. For example, the sub picture may include a plurality of objects (GRD-1, GRD-2, . . . , GRD-N); shift widths (108, 110) of the horizontal positions of the left and right ends of the objects are individually set and stored in the sub-picture data for displaying the objects for the right eye. A sub-picture superimposed on a stereoscopic video image can thereby be rendered in the depth direction, and the data size of the sub-picture and the amount of computation required for its display can be reduced.
    Type: Grant
    Filed: June 10, 2009
    Date of Patent: May 31, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kazuhiko Nakane
  • Patent number: 9355984
    Abstract: An embodiment method for fabricating electronic devices having two components connected by a metal layer includes applying a metal layer to each component and connecting the metal layers such that a single metal layer is formed.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: May 31, 2016
    Assignee: Infineon Technologies AG
    Inventors: Irmgard Escher-Poeppel, Eduard Knauer, Thomas Kunstmann, Peter Scherl, Raimund Foerg
  • Patent number: 9337405
    Abstract: A method for manufacturing a light emitting device comprises (a) preparing a structure including a substrate, a semiconductor layer formed on the substrate, and a p-side electrode and an n-side electrode formed on the semiconductor layer; (b) preparing a support member including a p-side wiring and an n-side wiring on the same surface thereof; (c) electrically connecting the p-side electrode and the n-side electrode of the structure to the p-side wiring and the n-side wiring of the support member, respectively, using an anisotropic conductive material containing conductive particles and a first resin; and after step (c), (d) removing the substrate from the structure.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: May 10, 2016
    Assignee: NICHIA CORPORATION
    Inventors: Takao Yamada, Ikuko Baike, Ryo Suzuki
  • Patent number: 9294755
    Abstract: An imaging platform minimizes inter-frame image changes when there is relative motion of the imaging platform with respect to the scene being imaged, where the imaging platform may be particularly susceptible to image change, especially when it is configured with a wide field of view or high angular rate of movement. In one embodiment, a system is configured to capture images and comprises: a movable imaging platform having a sensor that is configured to capture images of a scene, each image comprising a plurality of pixels; and an image processor configured to: digitally transform captured images with respect to a common field of view (FOV) such that the transformed images appear to be taken by a non-moving imaging platform, wherein the pixel size and orientation of pixels of each transformed image are the same. A method for measuring and displaying 3-D features is also described.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: March 22, 2016
    Assignee: RAYTHEON COMPANY
    Inventors: Ian S. Robinson, John D. Bloomer, Michael D. Vahey
  • Patent number: 9276060
    Abstract: A triode includes a semiconductor, a deep n-well, a p-well, an n+ doping region, and a doping region. The deep n-well is disposed adjacent to the semiconductor substrate. The p-well is included in the deep n-well and serves as a collector region of the triode. The n+ doping region serves as a base region of the triode. The p+ doping region serves as an emitter region of the triode. The deep n-well is coupled to the n+ doping region via at least one conducting channel.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: March 1, 2016
    Assignee: Fitipower Integrated Technology, Inc.
    Inventor: Chih-Nan Cheng
  • Patent number: 9269679
    Abstract: In a wafer level chip scale packaging technique for MEMS devices, a deep trench is etched on a scribe line area between two CMOS devices of a CMOS substrate at first. After bonding of the CMOS substrate with a MEMS substrate, the deep trench is opened by thin-down process so that CMOS substrate is singulated while MEMS substrate is not (partial singulation). Electrical test pad on MEMS substrate is exposed and protection material can be filled through the deep trench around bonding layers. After filling the protection material, the wafer is diced to form packaged individual chips with protection from environment outside bonding layer.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: February 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Chuan Teng, Jung-Huei Peng, Shang-Ying Tsai, Li-Min Hung, Yao-Te Huang, Chin-Yi Cho
  • Patent number: 9270891
    Abstract: A system and method are presented for estimating the orientation of a panoramic camera mounted on a vehicle relative to the vehicle coordinate frame. An initial pose estimate of the vehicle is determined based on global positioning system data, inertial measurement unit data, and wheel odometry data of the vehicle. Image data from images captured by the camera is processed to obtain one or more tracks, each track including a sequence of matched feature points stemming from a same three-dimensional location. A correction parameter determined from the initial pose estimate and tracks can then be used to correct the orientations of the images captured by the camera. The correction parameter can be optimized by deriving a correction parameter for each of a multitude of distinct subsequences of one or more runs. Statistical analysis can be performed on the determined correction parameters to produce robust estimates.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: February 23, 2016
    Assignee: Google Inc.
    Inventors: Dragomir Anguelov, Daniel Joseph Filip
  • Patent number: 9265408
    Abstract: In one embodiment, an apparatus may include an imager configured to generate a plurality of frames at a frame frequency greater than an electromagnetic energy emission pulse frequency of a medical device, wherein each frame of the plurality of frames may include a first plurality of rows. The apparatus may also include an electronic shutter module configured to offset a start time of each row of the first plurality of rows in each frame from the plurality of frames from a start time of an adjacent row in that same frame. The apparatus may further include an image processing module configured to generate a plurality of valid frames based on at least a portion of the plurality of frames, wherein the plurality of valid frames may include a frame frequency lower than the frame frequency of the plurality of frames.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: February 23, 2016
    Assignee: Boston Scientific Scimed, Inc.
    Inventors: Mark Modell, Jason Sproul
  • Patent number: 9265092
    Abstract: The invention relates to a heat transmission system based on electromagnetic radiation, which heat transmission system comprises an oven cavity and a foil with at least two layers, said at least two layers of the foil comprising a radiation-absorbing layer, wherein the wavelength spectre of the electromagnetic radiation of the radiation-absorbing layer and wavelength spectre of the electromagnetic radiation of the oven cavity are attuned to each other. The invention also relates to a foil for use in a heat transmission system, said foil comprising at least two layers, and wherein the wavelength spectre of the electromagnetic radiation of the foil is attuned to that of a heat source, eg the wavelength spectre of the electromagnetic radiation of an oven. The foil may be provided with a radiation-absorbing surface that may be configured both as a flexible foil and as an inflexible foil that may be of either metal or of a polymer, paper, cardboard or other materials that are based on wood.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: February 16, 2016
    Assignee: Aps af 28/8
    Inventors: Anita Schøning, Lars Schøning
  • Patent number: 9258573
    Abstract: The present invention relates to spatial prediction of pixels of a block, the block being a block of a digital image. In particular, for a block pixel at least one reference pixel(s) is selected and out of the selected reference pixel(s), the block pixel is predicted. In particular, the prediction of the block pixel is performed depending on the distance of this pixel to the reference pixel(s) from which it is to be predicted.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: February 9, 2016
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Virginie Drugeon, Thomas Wedi, Matthias Narroschke
  • Patent number: 9246061
    Abstract: A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-Type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface though which light is emitted. A copper layer has a first portion electrically connected to and opposing the bottom surface of the p-type layer. A dielectric wall extends through the copper layer to isolate a second portion of the copper layer from the first portion. A metal shunt electrically connects the second portion of the copper layer to the top surface of the n-type layer. P-metal electrodes electrically connect to the first portion, and n-metal electrodes electrically connect to the second portion, wherein the LED structure forms a flip chip. Other embodiments of the methods and structures are also described.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: January 26, 2016
    Assignee: Koninklijke Philips N.V.
    Inventors: Jipu Lei, Kwong-Hin Henry Choy, Yajun Wei, Stefano Schiaffino, Danel Alexander Steigerwald
  • Patent number: 9245988
    Abstract: An electrostatic discharge protection device has a substrate, a P-well, a N-well, and an isolation portion. The P-well and N-well formed in the substrate are neighboring to each other. Along a specific direction, the P-well has a first N-type, a first P-type, a second N-type, a second P-type, and a third N-type high doping regions sequentially located thereon, and the N-well has a third P-type, a fourth N-type, a fourth P-type, a fifth N-type, and a fifth P-type high doping regions sequentially located thereon. The first N-type, the third N-type, the first P-type, and the second P-type high doping regions are coupled to a ground end, the third P-type, the fifth P-type, the fourth N-type, and the fifth N-type high doping regions are coupled to a voltage supply end, and the second N-type and the fourth P type high doping regions are coupled to an input/output end.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: January 26, 2016
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventor: Che-Hong Chen
  • Patent number: 9245965
    Abstract: A structure including a first plurality of fins and a second plurality of fins etched from a semiconductor substrate, and a fill material located above the semiconductor substrate and between the first plurality of fins and the second plurality of fins, the fill material does not contact either the first plurality of fins or the second plurality of fins.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: January 26, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Balasubramanian S. Haran, Sanjay Mehta, Shom Ponoth, Ravikumar Ramachandran, Stefan Schmitz, Theodorus E. Standaert
  • Patent number: 9245828
    Abstract: A package and integrated circuit assembly is configured to perform signal conditioning on a signal. The assembly includes a line card having line card contacts that correspond to conductors in the line card connector. Two or more integrated circuits are configured to perform signal conditioning on the signal and the two or more integrated circuits are configured within a package into at least a first row and a second row on the package. The package includes a grid array of bonding pads to electrically connect to the two or more integrated circuits through bond wires or down bonds such that the structure of the grid array corresponds in physical arrangement or bond pad pitch to the line card contacts. This assembly also includes an electrical connection from the two or more integrated circuits to the line card through the package.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: January 26, 2016
    Assignee: Mindspeed Technologies, Inc.
    Inventors: Atul K. Gupta, Ryan S. Latchman, Marek S. Tlalka
  • Patent number: 9240325
    Abstract: A method includes making a gate stack on the surface of an active zone, including depositing a first dielectric layer; depositing a gate conductive layer; depositing a first metal layer; depositing a second metal layer; depositing a second dielectric layer; partially etching the gate stack for the formation of a gate zone on the active zone; making insulating spacers on either side of the gate zone on the active zone; making source and drain electrodes zones; making silicidation zones on the surface of the source and drain zones; etching, in the gate zone on the active zone, the second dielectric layer and the second metal layer with stopping on the first metal layer, so as to form a cavity between the insulating spacers; making a protective plug at the surface of the first metal layer of the gate zone on the active zone, where the protective plug fills the cavity.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: January 19, 2016
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS, COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventors: Sébastien Barnola, Yves Morand, Heimanu Niebojewski
  • Patent number: 9236336
    Abstract: Systems and methods are provided for an integrated circuit package. A plurality of electrical contacts are configured to provide a structure for electrically connecting the integrated circuit package to a printed circuit board. A package substrate includes at least one patterned metallic layer formed to electrically interconnect I/O contacts of an integrated circuit to the plurality of electrical contacts, and at least one generally uniform metallic layer having a plurality of voids that are respectively situated in axial alignment with corresponding ones of the electrical contacts, and one or more dielectric layers disposed between the plurality of electrical contacts and the metallic layers.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: January 12, 2016
    Assignee: MARVELL ISRAEL (M.I.S.L) LTD.
    Inventor: Eran Rotem
  • Patent number: 9220399
    Abstract: The invention relates to an endoscopic imaging system for observation of an operative site (2) inside a volume (1) located inside the body of an animal, comprising: Image capture means (3) intended to provide data on the operative site (2), Processing means (4) to process data derived from the image capture means, Display means (5) displaying data processed by the processing means (4), characterized in that: The image capture means (3) comprise at least two image capture devices that are independent and mobile relative to one another, the image capture devices being intended to be positioned inside the volume (1), and in that: The processing means (4) comprise computing means to obtain three-dimensional data on the observed operative site (2) from data provided by the image capture devices, and means to reconstruct a three-dimensional image of a region of interest of the operative site from the three-dimensional data obtained.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: December 29, 2015
    Assignee: CONSTELLIUM FRANCE
    Inventors: Philippe Cinquin, Sandrine Voros, Christophe Boschet, Céline Fouard, Alexandre Moreau-Gaudry
  • Patent number: 9219244
    Abstract: An organic light-emitting display apparatus basically comprises a thin film transistor, an organic light-emitting device and a pad electrode, and provides an improved adhesive force between a pad portion and an electrode and a stable signal supply. A method of manufacturing the organic light-emitting display apparatus comprises mask processes for forming on a curve layer of a thin film transistor, a pixel electrode and a first pad electrode, a gate electrode and a second pad electrode, contact holes and an interlayer insulating layer, source and drain electrodes and a third pad electrode, and a pixel define layer.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: December 22, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Won-Kyu Lee
  • Patent number: 9214601
    Abstract: An electroluminescent and photoluminescent white light emitting diode (LED) includes an electroluminescent light emitting structure, a first photoluminescent light emitting layer, a second photoluminescent light emitting layer and a red light emitting layer. The electroluminescent light emitting structure emits a violet light having a wavelength between 395 nm and 450 nm and an FWHM smaller than 25 nm. The first photoluminescent light emitting layer and the second photoluminescent light emitting layer are sequentially disposed on the electroluminescent light emitting structure. The first photoluminescent light emitting layer absorbs the violet light to generate a blue light. The second photoluminescent light emitting layer absorbs the violet light and the blue light to generate a green light. The red light emitting layer generates a red light. Accordingly, the violet light, the blue light, the green light and the red light are blended to form a white light having a high color rendering index.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: December 15, 2015
    Assignee: HIGH POWER OPTO, INC.
    Inventors: Fu-Bang Chen, Yen-Chin Wang, Wei-Yu Yen, Shih-Hsien Huang, Chih-Sung Chang
  • Patent number: 9165938
    Abstract: A semiconductor device includes a substrate having a cell region, wherein a contact region, page buffer regions, and a scribe lane region are defined around the cell region; a cell structure located in the cell region, including first conductive layers and first insulating layers which are alternately stacked, and having a non-stepped shape; a contact structure located in the contact region, including second conductive layers and second insulating layers which are alternately stacked, and having a stepped shape; a first dummy structure located in the page buffer region, including first sacrificial layers and third insulating layers which are alternately stacked, and having the non-stepped shape; and a second dummy structure located in the scribe lane region, including second sacrificial layers and fourth insulating layers which are alternately stacked, and having the stepped shape.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: October 20, 2015
    Assignee: SK Hynix Inc.
    Inventors: Won Ki Kim, Jong Man Kim