Abstract: An operational amplifier-based hysteresis comparator and a chip are provided. The hysteresis comparator includes: an input stage and an amplification stage. The input stage includes: a first input branch and a second input branch, where the first input branch generates a first current based on the first voltage, and the second input branch generates a second current based on the second voltage. The first current is connected with a first input terminal of the amplification stage, and the second current is connected with a second input terminal of the amplification stage. An output terminal of the amplification stage outputs a first level when the first current is greater than the second current, and outputs a second level when the first current is less than the second current. The present disclosure changes the hysteresis voltage generation mode, thereby reducing the instability caused by positive feedback.

Abstract: The present subject matter relates to active balun circuits. An active balun circuit includes a plurality of transistors; an output transmission line connected to output terminals of the transistors; an input transmission line; and a plurality of serial capacitors coupled to an input terminal of the transistors and the input transmission line.

Abstract: The disclosure disclose a control circuit and a lighting device, relates to a technical field of illumination. In the power-on process of the control circuit, the voltage input to the driving input terminal of the constant current driving module rises slowly, resulting in the current overshoot phenomenon of the light source load. In the control circuit disclosed by the present disclosure, because the output current of the first regulation output terminal is positively correlated with the output voltage of the voltage limiting terminal, and the output current of the second regulation output terminal is negatively correlated with the output voltage of the voltage limiting terminal, during the power-on process of the control circuit, that is, during the voltage at the voltage limiting terminal is changed from zero to the first threshold value, the current input to the driving input terminal can be relatively constant.

Abstract: A flame retardant lamp includes a lamp body, a printed circuit board (PCB), a power supply, a light-emitting plate, a controller, a driving circuit, and a first temperature sensor. The PCB, the power supply, and the light-emitting plate are disposed inside the lamp body, the controller and the driving circuit are disposed on the PCB, and the first temperature sensor is disposed on the light-emitting plate. The controller is electrically connected to the light-emitting plate through the driving circuit, the first temperature sensor is electrically connected to an input end of the controller, and the power supply is electrically connected to a power supply end of the PCB.

Abstract: An electronic device and a method for overcurrent detection are disclosed herein. The electronic device causes a high-side offsetting voltage drop and converts a voltage difference between a first voltage at an input terminal of an upper-bridge power component of a power stage and a sum of a first balancing voltage drop and the high-side offsetting voltage drop into a first current. The electronic device further converts a voltage difference between a second voltage of an output terminal of the upper-bridge power component and a second balancing voltage drop into a second current, compares the first current and the second current, and generates a high-side overcurrent protection (OCP) signal with logic high for a driver of the power stage when the first current is stronger than the second current, such that the driver turns off the upper-bridge power component accordingly.

Abstract: A comparator is presented. The comparator includes an input port for receiving an input voltage; an output port for providing an output voltage; a resistive divider, first and second transistors, and a differential amplifier. The resistive divider has a first node for providing a first voltage and a second node for providing a second voltage. The first transistor has a control terminal coupled to the first node, a first terminal coupled to the input port, and a second terminal coupled to a common node. The second transistor has a control terminal coupled to the second node, a first terminal coupled to the input port, and a second terminal coupled to the common node. The differential amplifier has a first input coupled to the first terminal of the first transistor, a second input coupled to the first terminal of the second transistor and an output coupled to the output port.

Abstract: An apparatus, including: a clock gating circuit (CGC), including: a clock gating device configured to selectively gate/pass a selected clock signal based on an enable signal to generate an output clock signal; and a clock selection circuit configured to select a non-complementary clock signal or a complementary clock signal to generate the selected clock signal based on the output clock signal and the non-complementary clock signal or the complementary clock signal.

Abstract: The invention provides a light generating system (1000) comprising one or more first light generating devices (110), one or more second light generating devices (120), and one or more third light generating devices (130), wherein: —the one or more first light generating devices (110) are configured to generate white first device light (111) having a first color rendering index CRI1 and a first correlated color temperature Tc1; —the one or more second light generating devices (120) are configured to generate white second device light (121) having a second color rendering index CRI2 and a second correlated color temperature Tc2; —the one or more third light generating devices (130) are configured to generate third device light (131) having a third dominant wavelength ?d3 selected from the range of 470-500 nm; —CRI1?CRI2?10; CRI1?85; Tc2?Tc1?1000K; Tc1?3500K; and Tc2?3000K; and—the light generating system (1000) is configured to generate system light (1001) comprising one or more of the first device light (111),

Abstract: A method for determining temperature of a chip, includes generating a first voltage and a second voltage using a pair of bipolar-junction transistors, and generating a third voltage using another bipolar-junction transistor. When a most recent bit of a bitstream is a logic-zero, the difference between the first and second voltages is sampled using a switched-capacitor input-sampling circuit, and a difference between the first and second voltages is integrated, to produce a proportional-to-absolute-temperature voltage. The proportional-to-absolute-temperature voltage is quantized to produce a next bit of the bitstream. When the most recent bit of the bitstream is a logic-one, the third voltage is sampled using the switched-capacitor input-sampling circuit, and the third voltage is integrated, to produce a complementary-to-absolute-temperature voltage. The complementary-to-absolute-temperature voltage is quantized to produce a next bit of the bitstream.

Abstract: A high-frequency power supply apparatus includes the following elements. A first power supply supplies first power to a load by outputting a first voltage whose fundamental frequency is higher than a second voltage output by a second power supply. A period signal generation circuit generates a period signal matching a frequency and a phase of the second voltage. A waveform control circuit generates a modulation signal for performing frequency modulation on a fundamental wave signal of the first voltage, and adjusts an output timing of the modulation signal in accordance with a timing of the period signal. The first power supply generates a first frequency signal by performing frequency modulation on the fundamental wave signal of the first voltage by using the modulation signal. The first power supply performs power amplification on the first frequency signal and outputs, to the load, the first frequency signal as first power.

Abstract: An electronic device may include wireless circuitry having a radio-frequency mixer. The mixer may include a first pair of mixer transistors configured to receive an oscillating signal, a second pair of mixer transistors configured to receive the oscillating signal, and a bias circuit configured to receive the oscillating signal and to generate a corresponding output voltage for controlling an amount of current flowing through the first and second pairs of mixer transistors. The bias circuit can be configured as a replica envelope detection circuit. The bias circuit can include a pair of bias transistors coupled to a tail transistor that receives the output voltage of the replica envelope detection circuit.

Abstract: A flip-flop includes a first input circuit, a first NOR logic gate, a stacked gate circuit, a first NAND logic gate and an output circuit. The first input circuit generates a first signal responsive to at least a first data signal, a first or a second clock signal. The first NOR logic gate is coupled between a first and a second node, and generates a second signal responsive to the first signal and a first reset signal. The stacked gate circuit is coupled between the first and a third node, and generates a third signal responsive to the first signal. The first NAND logic gate is coupled between the third and a fourth node, and generates a fourth signal responsive to the third signal and a second reset signal. The output circuit is coupled to the fourth node, and generates a first output signal responsive to the fourth signal.

Abstract: The present application provides a level shift circuit, an integrated circuit, and an electronic device. The level shift circuit comprises: an input module, configured to output a first control signal according to a first power supply voltage signal, first and second input voltages, inverted voltages of the first and second input voltages that received; a control voltage generation module, configured to receive the first control signal, and generate a plurality of node voltages according to the first control signal and a second power supply voltage signal; and output control modules, configured to generate first to fourth output signals according to the node voltages and the first power supply voltage signal, or generate fifth to eighth output signals according to the second power supply voltage signal and the node voltages.

Abstract: An LED driver includes an operational amplifier (OP), N current driving circuits, and a resistor circuit. The OP compares a reference voltage with a feedback voltage to generate a control voltage. Each current driving circuit is coupled with an LED, and includes: an NMOS transistor including a drain, a source, and a gate, and being turned on according to the control voltage in an enablement mode and turned off according to the voltage of a ground terminal in a disablement mode, wherein the drain is coupled with the LED and the voltage at the source is the feedback voltage; and a switch circuit coupling the OP with the gate in the enablement mode, and coupling the ground terminal with the gate in the disablement mode. The resistor circuit is coupled between the source and the ground terminal and controls the current passing through the N current driving circuits.

Abstract: A system and method for accurately determining a distance between two network devices using a Channel Sounding application is disclosed. The network devices each guarantee a fixed phase relationship between the transmit circuit and the receive circuit. In one embodiment, this is achieved by disposing the divider outside the phase locked loop and using the output of the divider to create the clocks for both the transmit circuit and receive circuit. In another embodiment, one or more dividers are disposed outside the phase locked loop, each having a reset, such that they can be initialized to a predetermined state. Further, by utilizing a divider with a reset, the quadrature signal generator is guaranteed to output clocks for the transmit circuit and the receive circuit that have a constant phase relationship.

Abstract: Disclosed are a fan and lamp control circuit, a fan and lamp device, and a fan and lamp system. The fan and lamp control circuit includes: a voltage conversion circuit configured to convert a voltage output by an AC power supply to obtain a converted voltage and output the converted voltage; an LED drive circuit, configured to drive the LED lamp to work and adjust the brightness and color temperature of the LED lamp according to the received LED control signal; a fan drive circuit, configured to drive the fan to work and adjust the speed of the fan according to the received fan control signal; and a main control circuit, the output end of the main control circuit is electrically connected to the input ends of the LED drive circuit and the fan drive circuit, for sending the LED control signal and the fan control signal.

Abstract: Techniques are described herein to enhance capability of floating level translators. For example, increased headroom is accomplished by adaptively bypassing the protection elements of the voltage level translator. In an example, a floating level translator can translate an input signal from a low-voltage domain to a high-voltage domain. A bypass circuit is coupled across the protection elements. The bypass circuit selectively engages during low-voltage operation (e.g., thereby providing a lower loss path relative to loss caused by the high-voltage protection elements and thus increasing the headroom swing), and disengages responsive to the high-voltage reference rail of the high-voltage domain exceeding a threshold or otherwise being high enough (e.g., greater than the potential of the low-voltage domain power rail). The bypass circuit can be implemented in a relatively low-complexity manner (e.g., back-to-back high-voltage FETs) without additional signals to control low-voltage capability.

Abstract: An integrated circuit includes a power-on reset (POR) circuit, a watchdog timer, a first AND gate and a power management control circuit. The POR circuit is used to receive an input voltage to generate a POR signal and generate a clock signal. The watchdog timer is used to generate a timeout signal according to the clock signal when the POR signal has an enabling voltage, the clock signal enabling generation of timeout pulses in the timeout signal at predetermined time intervals. The first AND gate including a first input terminal for receiving the POR signal; a second input terminal for receiving the timeout signal; and an output terminal for outputting a reset signal according to the POR signal and the timeout signal. The power management control circuit is used to reset an output current in response to a reset pulse in the reset signal.

Abstract: A driving output circuit, a chip, and a driving output method are provided; the driving output circuit includes: a timer for outputting a timing signal; a bootstrap module for generating a first turn-on voltage based on an input signal; a charge pump for generating a second turn-on voltage based on the timing signal; a driving module including an upper driving MOSFET and a lower driving MOSFET connected to the upper driving MOSFET, and the upper driving MOSFET is connected to the lower driving MOSFET at a signal output; the first turn-on voltage and the second turn-on voltage are both used to turn on the upper driving MOSFET and/or the lower driving MOSFET to cause the signal output to output an output signal. The present disclosure provides a dynamic hybrid driving output circuit, which has improved gate oxide reliability and an enhanced anti-leakage function when not powered.

Abstract: A light-emitting diode (LED) array includes an array of pixel assemblies and a pulse width modulator. The pulse width modulator generates pulse width modulation (PWM) signals for controlling a duty cycle of each of the pixels. The pixel assemblies each include an LED, a switching circuit, and a close loop circuit. The switching circuit receives a PWM signal and alternately turns on and off the LED based on the PWM signal. The close loop circuit regulates an LED current provided by the switching circuit to the LED based on a feedback signal received from the switching circuit. The close loop circuit in one pixel assembly may receive a reference current from a close loop circuit of another pixel assembly.