Patents Examined by Long Nguyen
  • Patent number: 10389307
    Abstract: A power amplifier circuit includes a first transistor, a second transistor, a first bias circuit supplying a first bias current or voltage, a second bias circuit supplying a second bias current or voltage, a first inductor, and a first capacitor. A power supply voltage is supplied to a collector of the first transistor, and an emitter thereof is grounded. A radio frequency signal and the first bias current or voltage are supplied to a base of the first transistor. The power supply voltage is supplied to a collector of the second transistor, and an emitter thereof is connected to the collector of the first transistor via the first capacitor and is grounded via the first inductor. The second bias current or voltage is supplied to a base of the second transistor. An amplified radio frequency signal is output from the collector of the second transistor.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: August 20, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Masatoshi Hase, Yuri Honda, Kazuo Watanabe, Takashi Soga
  • Patent number: 10374589
    Abstract: A temperature detecting circuit comprising: a comparator, comprising a first comparing terminal and a second comparing terminal; a time interval computing unit; a switch module, coupled to the first comparing terminal and the second comparing terminal, comprising a reference voltage terminal coupled to a reference voltage source, and comprising a first input terminal, a second input terminal and a third input terminal; a first current source, comprising a first charging terminal coupled to the first input terminal and the second input terminal; a first capacitor, coupled to the first current source at the first charging terminal; a capacitance adjusting unit, coupled to the first capacitor; a second current source, comprising a second charging terminal coupled to the third input terminal, wherein the second current source is a current source which provides a constant current; and a second capacitor, coupled to the second current source at the second charging terminal.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: August 6, 2019
    Assignee: PixArt Imaging Inc.
    Inventors: Wooi Kip Lim, Yong Yeap Tan
  • Patent number: 10374603
    Abstract: In one embodiment, a (pre)driver circuit includes first and a second output terminal for driving an electronic switch that includes a control terminal and a current path through the switch. The arrangement can operate in one or more first driving configurations (e.g., for PMOS), with the first and second output terminals are coupled to the current path and the control electrode of the electronic switch, respectively, and one or more second driving configurations (e.g., for NMOS, both HS and LS), wherein the first and second output terminals of the driver circuit are coupled to the control electrode and the current path of the electronic switch, respectively.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: August 6, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Daniele Zella, Vanni Poletto, Mauro Foppiani
  • Patent number: 10374594
    Abstract: The semiconductor device according to one embodiment includes a power transistor and a sense transistor connected in parallel with each other, a first operational amplifier having a non-inverting input terminal connected to an emitter of the sense transistor and an inverting input terminal connected to an emitter of the power transistor, a resistor element having one end connected to the emitter of the sense transistor and another end connected to a first node, and an adjustment transistor placed between the first node and a low-voltage power supply. The first operational amplifier adjusts a current flowing through the adjustment transistor so that an emitter voltage of the power transistor and an emitter voltage of the sense transistor are substantially the same.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: August 6, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shunichi Kaeriyama
  • Patent number: 10367482
    Abstract: A Schmitt trigger circuit includes a first circuit; a second circuit; a first switch; a third circuit; and a second switch. The first circuit output the output signal of a second or first logical level. The second circuit is coupled to a first potential node at a first end, and sends a current between the first end and a second end based on the output signal. The first switch electrically couples or uncouples the second end and a first node based on a selection signal. The third circuit is coupled to a second potential node at a third end, and sends a current exclusively with the second circuit between the third end and a fourth end based on the output signal. The second switch electrically couples or uncouples the fourth end and the first node based on the selection signal.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: July 30, 2019
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Takayuki Hiraoka
  • Patent number: 10365682
    Abstract: A network including a current-mode transmitter configured to receive a first voltage and output a first current to a first node in accordance with a first control signal. A transmission line is configured to conduct a signal transmission between the first node and a second node, wherein the transmission line comprises an internal tapping point at a third node. A first transimpedance amplifier is configured to receive a second current from the second node and output a second voltage in accordance with a second control signal. Further; a second transimpedance amplifier is configured to receive a third current from the third node and output a third voltage in accordance with a third control signal.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: July 30, 2019
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 10359794
    Abstract: Bias circuit and a bias generator circuit comprising such a bias circuit. The bias circuit (10, 11) comprises a switched capacitor resistor circuitry (C1, C2, M12-M17), and an operational amplifier (M1-M4, M10) with an input differential transistor pair (M1, M2). The bias circuit further comprises additional source follower transistors (M5, M6) associated with the first and second input differential transistors (M1, M2).The bias generator circuit has a PMOS switched capacitor reference circuit (11) and a NMOS switched capacitor reference circuit (10) and a transconductor reference cell (15). The transconductor reference cell (15) is a replica of a basic reference cell used in a further circuit.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: July 23, 2019
    Assignee: Qorvo US, Inc.
    Inventor: Erdogan Ozgur Ates
  • Patent number: 10361669
    Abstract: An output circuit includes a first transistor, a second transistor, an operational amplifier that outputs a control voltage, and a switch circuit that controls voltage output in accordance with a control signal. When the control signal is in a first state, the switch circuit supplies the control voltage to the gate of the first transistor to turn on the first transistor and electrically connects the drain of first transistor to the operational amplifier so that a first output voltage is output from the drain of the first transistor. When the control signal is in a second state, the switch circuit supplies the control voltage to the gate of the second transistor to turn on the second transistor and electrically connects the drain of the second transistor to the operational amplifier so that a second output voltage is output from the drain of the second transistor.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: July 23, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yusuke Shimamune
  • Patent number: 10348292
    Abstract: A power-on reset signal generating apparatus and a voltage detection circuit thereof are provided. The voltage detection circuit includes a latch circuit, a pre-charge circuit, a pull-down switch and an output stage circuit. The pull-down circuit is turned on or cut off according to the power-on reset signal. The pre-charge circuit operates a pre-charge action according to a power-on reset signal or a power supply voltage. The output stage circuit receives the power supply voltage, based on the power supply voltage, generates a detection output voltage according to an input end of the inverter and the power-on reset signal.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: July 9, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Jyun-Yu Lai, Hsing-Yu Liu, Ya-Chun Chang
  • Patent number: 10339986
    Abstract: A data latch circuit and a pulse signal generator thereof are provided. The pulse signal generator includes a first buffer, a second buffer, a pull-up switch and an output buffer. The first buffer generates a first buffering signal according to an input signal and a feedback signal. The second buffer generates a second buffering signal according to the input signal and the first buffering signal. The pull-up switch pulls up the second buffering signal according to the first buffering signal. The output buffer generates at least one output pulse signal according to the second buffering signal. The output buffer further outputs the at least one output pulse signal to the first buffer to be the feedback signal.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: July 2, 2019
    Assignee: DigWise Technology Corporation, LTD
    Inventors: Jingjie Wu, Chih-Wen Yang, Wen-Pin Hsieh
  • Patent number: 10339914
    Abstract: A device voltage shifter includes a first voltage reference node, a second voltage reference node, an output node and a clamp node. A first high-voltage switching transistor of the voltage shifter has a first conduction terminal coupled to the first voltage reference node and a second conduction terminal coupled to the clamp node. A second high-voltage switching transistor of the voltage shifter has a first conduction terminal coupled to the clamp node and a second conduction terminal coupled to the second voltage reference node. A third high-voltage switching transistor of the voltage shifter has a first conduction terminal coupled to the first voltage reference node, a control terminal coupled to the clamp node, and a second conduction terminal coupled to the output node. A voltage regulator of the voltage shifter is coupled between the output node and the clamp node.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: July 2, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Matteo Albertini, Sandro Rossi
  • Patent number: 10333498
    Abstract: An integrated circuit includes a plurality of positive edge-triggered master-slave flip-flop circuits sharing a clock signal. At least one of the positive edge-triggered master-slave flip-flop circuits includes; an input stage that provides a first output signal generated from an input signal in response to the clock signal and an inverted clock signal, a first inverting circuit that generates the inverted clock signal by delaying the clock signal, a transmission gate that receives a second output signal and generates a final output signal, and a second inverting circuit that receives the first output signal and generates the second output signal from the first output signal. The clock signal is applied to an NMOS transistor of the transmission gate and a PMOS transistor of the input stage, and the inverted clock signal is applied to a PMOS transistor of the transmission gate and an NMOS transistor of the input stage.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: June 25, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min Su Kim, Jong Woo Kim, Ji Kyum Kim
  • Patent number: 10333529
    Abstract: In one embodiment, a differential to single ended conversion circuit is configured to convert a differential signal to a single ended signal without using an operational amplifier and without using a current source to charge a capacitor.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: June 25, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Masayuki Kanematsu
  • Patent number: 10333502
    Abstract: Various embodiments provide for a level shifter with sub-threshold voltage functionality, which permits the level shifter to operate even when a voltage supply to the level shifter falls below a normal operational voltage range of one or more devices (e.g., transistors) within the level shifter. A level shift of an embodiment may operate when a voltage supply falls below a normal operational range in order to save power, which can be useful with respect to battery-operated devices, such an Internet of Things (IoT) sensor.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: June 25, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Abhinav Srivastava, Vinod Kumar
  • Patent number: 10326447
    Abstract: Disclosed herein is a latch circuit capable of preventing an output failure caused due to simultaneous transition of a control signal and an input signal. The latch circuit according to the present invention generates a separate control adjustment signal CTR using the control signal Control and the input signal In and uses the control adjustment signal CTR, instead of the control signal for a latch operation. Accordingly, when the control signal and the input signal transition at the same time, the control adjustment signal is processed not to transition during a transition interval of the input signal, thereby preventing a metastability problem that occurred in the existing latch circuit.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: June 18, 2019
    Assignee: ADTECHNOLOGY CO., LTD.
    Inventors: Young Seung Kim, Scott Seungmoon Yoo, Min Chul Jung, Jun Suk Kim
  • Patent number: 10324485
    Abstract: A body bias voltage generating circuit for supplying a body bias voltage to a body of a transistor of a functional circuit is provided, including: a first transistor and a second transistor connected in series between a supply voltage terminal and a ground terminal, wherein a control terminal of the first transistor is coupled with a control terminal of the second transistor; a third transistor, wherein a body of the third transistor is electrically coupled with any one of the body of the first transistor and the second transistor, and a terminal of the third transistor is coupled with the body of the third transistor; and a resistance element coupled between the terminal of the third transistor and a current input terminal of the first transistor or a current output terminal of the second transistor. The terminal of the third transistor is the body bias voltage.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: June 18, 2019
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Ming-Hsin Huang
  • Patent number: 10326481
    Abstract: A power amplification module includes a first amplification transistor that receives a first signal outputs an amplified second signal from the collector thereof; and a bias circuit that supplies a bias current to the base of the first amplification transistor. The first bias circuit includes a first transistor that is diode connected and is supplied with a bias control current; a second transistor that is diode connected, the collector thereof being connected to the emitter of the first transistor; a third transistor, the base thereof being connected to the base of the first transistor, and the bias current being output from the emitter thereof; a fourth transistor, the collector thereof being connected to the emitter of the third transistor and the base thereof being connected to the base of the second transistor; and a first capacitor between the base and the emitter of the third transistor.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: June 18, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Masatoshi Hase
  • Patent number: 10326431
    Abstract: A novel clock level-shifter to reduce duty-cycle distortion across wide input-output voltage operating range is disclosed. In some implementations, a level shifter includes an input stage coupled to a first power supply to receive an input signal, an output stage coupled to a second power supply to generate an output signal, and a first switch coupled directly between the output stage and the second power supply, wherein the input signal turns on or off the first switch. In some implementations, the first switch has a gate, a source, and a drain, the source being coupled to the second power supply, the drain being coupled to the output stage, and the gate being driven directly by the input signal.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: June 18, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Pratik Rajeshbhai Patel, Percy Tehmul Marfatia, Rajagopal Narayanan
  • Patent number: 10326450
    Abstract: A method and circuit for implementing a level shifter for translating logic signals to output voltage analog levels, and a design structure on which the subject circuit resides are provided. The circuit includes a level shifter resistor divider string of a plurality of series connected resistors, the level shifter resistor divider string is connected between an analog voltage rail and an analog ground. A plurality of level shifter cascaded inverters are connected between respective resistors of the level shifter resistor divider string and an analog voltage rail and an analog ground. An output of the level shifter is programmed by the level shifter resistor divider string connected to the cascaded inverters.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Andrew D. Davies, David M. Friend, Grant P. Kesselring, James D. Strom
  • Patent number: 10312902
    Abstract: This application discusses techniques for providing a power-on reset (POR) circuit. The techniques take advantage of the small size of active devices, consume very little current and can use a native NMOS transistor to provide a stable reference over temperature and voltage variations.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: June 4, 2019
    Assignee: Analog Devices Global
    Inventors: Amit Kumar Singh, Sriram Ganesan