Patents Examined by Long Nguyen
  • Patent number: 10784861
    Abstract: Systems, methods, and apparatus for biasing a high speed and high voltage driver using only low voltage transistors are described. The apparatus and method are adapted to control biasing voltages to the low voltage transistors such as not to exceed operating voltages of the low voltage transistors while allowing for DC to high speed operation of the driver at high voltage. A stackable and modular architecture of the driver and biasing stages is provided which can grow with a higher voltage requirement of the driver. Capacitive voltage division is used for high speed bias voltage regulation during transient phases of the driver, and resistive voltage division is used to provide bias voltage at steady state. A simpler open-drain configuration is also presented which can be used in pull-up or pull-down modes.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: September 22, 2020
    Assignee: pSemi Corporation
    Inventor: Gary Chunshien Wu
  • Patent number: 10778204
    Abstract: A comparator circuit with low power consumption and low kickback noise includes a first dynamic comparator and a second dynamic comparator. The first dynamic comparator is a pre-amplifier for the second dynamic comparator. An enable switch which is connected to the first dynamic comparator has a control terminal connected to a resistance device. The resistance device and the enable switch form a RC delay circuit to reduce the kickback noise of the comparator circuit. Since the comparator circuit is composed of dynamic comparators, the power consumption of the comparator circuit is lower.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: September 15, 2020
    Assignee: National Chiao Tung University
    Inventors: Shih-Hsing Wang, Chung-Chih Hung
  • Patent number: 10778262
    Abstract: A power amplification module includes a first amplification transistor that receives a first signal outputs an amplified second signal from the collector thereof; and a bias circuit that supplies a bias current to the base of the first amplification transistor. The first bias circuit includes a first transistor that is diode connected and is supplied with a bias control current; a second transistor that is diode connected, the collector thereof being connected to the emitter of the first transistor; a third transistor, the base thereof being connected to the base of the first transistor, and the bias current being output from the emitter thereof; a fourth transistor, the collector thereof being connected to the emitter of the third transistor and the base thereof being connected to the base of the second transistor; and a first capacitor between the base and the emitter of the third transistor.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: September 15, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Masatoshi Hase
  • Patent number: 10778092
    Abstract: The present disclosure provides a negative voltage generating circuit having an automatic voltage adjustment function, including a negative voltage generating circuit and a feedback control module. The negative voltage generated by the negative voltage generating circuit is adjusted by the feedback control module. The negative voltage generating circuit having the automatic voltage adjustment function of the present disclosure can automatically adjust the charge current of the charge pump according to the load current, thereby realizing the stability of the output voltage, such that the traditional analog circuit structure can work normally under the extremely low power supply voltage, and is particularly suitable for the deep submicron process. The present disclosure also realizes the digital adjustment of the output voltage, the negative voltage output is no longer single, and can be adjusted according to actual needs.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: September 15, 2020
    Assignee: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Rongbin Hu, Yonglu Wang, Zhengping Zhang, Jian'an Wang, Guangbing Chen, Dongbing Fu, Yuxin Wang, Hequan Jiang, Gangyi Hu
  • Patent number: 10771057
    Abstract: A semiconductor device of embodiments includes a first normally-off transistor having a first electrode, a second electrode, and a first control electrode, a normally-on transistor having a third electrode electrically connected to the second electrode via a first wiring, a fourth electrode, and a second control electrode, a second normally-off transistor having a fifth electrode, a sixth electrode electrically connected to the third electrode via a second wiring, and a third control electrode, a first diode having a first anode electrically connected to the second control electrode and a first cathode electrically connected to the third electrode, and a capacitor having a first end portion connected to the first anode and the second control electrode and a second end portion.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: September 8, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Akira Yoshioka, Toru Sugiyama, Masaaki Iwai, Naonori Hosokawa, Masaaki Onomura, Hung Hung, Yasuhiro Isobe
  • Patent number: 10763855
    Abstract: A circuit includes a high voltage (HV) transistor having a first current electrode, a second current electrode, and a control electrode coupled to receive a control signal. The HV transistor is configured and arranged to be non-conductive when the control signal is at a first state and conductive when the control signal is at a second state. A low voltage (LV) transistor is coupled to the first current electrode of the HV transistor. An HV pad is coupled to the second current electrode of the HV transistor. An operating voltage rating of the HV pad exceeds an operating voltage rating of the LV transistor. A secondary electrostatic discharge protection device is coupled between the second current electrode of the HV transistor and a voltage supply terminal.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 1, 2020
    Assignee: NXP USA, INC.
    Inventors: Ashutosh Jain, Michael A Stockinger, Stefano Pietri, Jaideep Banerjee, Ateet Omer
  • Patent number: 10763840
    Abstract: A comparator circuit includes a first comparator, a second comparator and an inverter. The first comparator includes two N-channel metal-oxide-semiconductor (NMOS) transistors, two first P-channel metal-oxide-semiconductor (PMOS) transistors and two second PMOS transistors. A gate of the NMOS transistors respectively receives first and second voltages, and sources of the first PMOS transistors are connected to first and second resistors, respectively. The first comparator outputs differential output signals from drains of the NMOS transistors according to the voltage difference between the first and second voltages. An output of the second comparator is connected to gates of the first PMOS transistors of the first comparator. An input of the inverter is connected to the output of the second comparator, and an output of the inverter is connected to gates of the PMOS transistors.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: September 1, 2020
    Assignee: LITE-ON SINGAPORE PTE. LTD.
    Inventors: Meng-Tong Tan, You-Fa Wang
  • Patent number: 10756715
    Abstract: A pulse generation circuit has: an edge detector detecting a pulse edge in an input signal to generate edge detection signals; a clock generator generating a clock signal according to the edge detection signals; a frequency divider dividing the frequency of the clock signal to generate a frequency-divided clock signal; an input pad for receiving a test mode switch signal from a tester; and an output pad for outputting the frequency-divided clock signal to the tester. The edge detector can generate the edge detection signals by detecting a pulse edge not in the input signal but in the clock signal or in the inverted clock signal obtained by inverting the logic level of the clock signal when the test mode switch signal is being fed in. The signal delay time in the edge detector is adjustable according to the period of the frequency-divided clock signal as measured by the tester.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: August 25, 2020
    Assignee: Rohm Co., Ltd.
    Inventor: Masahiko Arimura
  • Patent number: 10749508
    Abstract: A signal converter, a duty-cycle corrector, and a differential clock generator are provided. The differential clock generator includes the signal converter and the duty-cycle corrector. The signal converter is capable of calibrating skew distortion, and the duty-cycle corrector is capable of calibrating duty-cycle distortion. With the signal converter and the duty-cycle corrector, the differential clock generator can be applied to communication devices operating at high frequency.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: August 18, 2020
    Assignee: Faraday Technology Corp.
    Inventor: Vinod Kumar Jain
  • Patent number: 10749527
    Abstract: A level shifting circuit includes a level shifting portion configured to receive an input signal and generate an output signal, and a current adjustment circuit connected between the level shifting portion and a drive high voltage node at which a drive high voltage is applied. The current adjustment circuit is configured to adjust an amount of current provided from the drive high voltage node to the level shifting portion.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dalhee Lee, Jintae Kim, Jaeha Lee
  • Patent number: 10742210
    Abstract: A drive circuit drives switches that are connected to each other in parallel. The drive circuit includes individual discharge paths, a common discharge path, blocking units, a discharge switch, off-holding switches, and a drive control unit. The drive control unit selects, as target switches to be driven to be turned on, at least two switches among the switches. The at least two switches include a first switch and a second switch. The first switch is last to be switched to an off-state among the at least two switches that are selected as the target switches and switched to an on-state. The second switch is other than the first switch among the at least two switches. The off-holding switches includes a first off-holding switch and a second off-holding switch. After switching the second off-holding switch to an on-state, the drive control unit switches the discharge switch to an on-state.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: August 11, 2020
    Assignee: DENSO CORPORATION
    Inventors: Tomotaka Suzuki, Yusuke Shindo, Yasutaka Senda, Ken Toshiyuki
  • Patent number: 10734995
    Abstract: An output circuit may be provided with: input and output terminals; a ground terminal shared by both an input side and an output side; a first switching element of n-channel type having first positive and negative electrodes, and a first gate; a second switching element of the n-channel type having second positive and negative electrodes, and a second gate; a diode; and a resistive element; in which the first positive electrode is connected with a power source, the first negative electrode is connected with the output terminal, anode of the diode is connected with the first negative electrode, cathode of the diode is connected with the first gate, the resistive element is connected between the source and the first gate, the second positive electrode is connected with the first gate, the second negative electrode is connected with the ground terminal, and the second gate is connected with the input terminal.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: August 4, 2020
    Assignee: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO
    Inventors: Norikazu Oota, Kanae Murata, Takashi Ozaki
  • Patent number: 10725491
    Abstract: Methods, systems, and apparatus to correct gate bias for a diode-connected transistor are disclosed. An example apparatus includes a first resistor including a first resistor terminal and a second resistor terminal; a second resistor including a first resistor terminal and a second resistor terminal; a first transistor including a current terminal and a gate terminal, the current terminal of the first transistor coupled to the first resistor terminal of the first resistor and the gate terminal of the first transistor is coupled to the second resistor terminal of the first resistor; and a second transistor including a first current terminal and a second current terminal, the first current terminal of the second transistor coupled to the gate terminal of the first transistor, and the second current terminal of the second transistor coupled the first current terminal of the second resistor.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: July 28, 2020
    Assignee: Texas Instruments Incorporated
    Inventor: Gregory Wallis Collins
  • Patent number: 10715137
    Abstract: Devices, systems, and methods are provided for generating a high, dynamic voltage boost. An integrated circuit (IC) includes a driving circuit having a first stage and a second stage. The driving circuit is configured to provide an overdrive voltage. The IC also includes a charge pump circuit coupled between the first stage and the second stage. The charge pump circuit is configured generate a dynamic voltage greater than the overdrive voltage. The IC also includes a bootstrap circuit coupled to the charge pump circuit, configured to further dynamically boost the overdrive voltage of the driving circuit.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chan-Hong Chern, Tysh-Bin Liu, Kun-Lung Chen
  • Patent number: 10715129
    Abstract: A switching element driving device includes a main on switch that is connected to gates of a first and second IGBTs and that, when brought into a conductive state, turns on the first and second IGBTs, diodes each disposed between the main on switch and one of the gates of the first and second IGBTs, the diodes having a forward direction from the main on switch to the gates of the first and second IGBTs, an on sub-switch that is connected to the gate of the second IGBT and that, when brought into the conductive state, turns on the second IGBT, and a control circuit that controls the conductive state and a non-conductive state of the main on switch and the on sub-switch.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: July 14, 2020
    Assignee: DENSO CORPORATION
    Inventor: Akifumi Araragi
  • Patent number: 10715027
    Abstract: A driver circuit includes a gate capacitance discharge circuit that reduces a resistance value of a resistor for pulling down the gate of a PMOSFET at the output stage for a predetermined period at the timing when an NMOSFET turns on and a pull-down resistor switching circuit that switches pull-down resistors of the gate capacitance discharge circuit, based on a divided voltage into which voltage of the high voltage power supply system is divided, in which the pull-down resistor switching circuit, when the divided voltage is higher than a reference voltage Vref, switches the pull-down resistor for the predetermined period to a resistor and, when the divided voltage is the reference voltage Vref or lower, switches the pull-down resistor to a resistor having a higher resistance value than the resistor.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: July 14, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takato Sugawara
  • Patent number: 10707865
    Abstract: Devices and methods are provided where a control terminal resistance of a transistor device is set depending on operating conditions within a specified range of operating conditions.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: July 7, 2020
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Anton Mauder, Martina Seider-Schmidt, Hans-Joachim Schulze, Oliver Hellmund, Sebastian Schmidt, Peter Irsigler
  • Patent number: 10707863
    Abstract: A power-on reset circuit is provided. During a power-on process of the power-on reset circuit, a threshold voltage of an output signal rstn jumping from a low level to a high level is adjusted by clamp of a voltage at a node c and voltage division between a first resistor and a second resistor, and is controlled to be greater than a threshold voltage of a metal oxide semiconductor device. During a power-off process of the power-on reset circuit, a threshold voltage of the output signal rstn jumping from the high level to the low level is adjusted by increasing a voltage at a node d by means of a third resistor and voltage division between the first resistor and the third resistor, and is controlled to be greater than the threshold voltage of the metal oxide semiconductor device.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: July 7, 2020
    Assignee: LONTIUM SEMICONDUCTOR CORPORATOIN
    Inventors: Jiaxi Fu, Cheng Tao, Xiangyu Ji, Feng Chen
  • Patent number: 10707855
    Abstract: A pulse modulation circuit with a high-frequency-limiting function, including a comparator, an RS trigger, a switching triode, a NAND gate, a NOR gate, and a charging capacitor. A capacitor charging time is controlled by adjusting a bias current IB1, a bias current IB2, a reference voltage V1, and a reference voltage V2 or adjusting values of capacitors C1 and C2. In this way, a highest output frequency of a pulse generator is limited, so as to reduce hardware system overheads.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: July 7, 2020
    Assignee: CHONGQING PASSION CHUANGZHI MICROELECTRONICS CO., LTD.
    Inventor: Fang Tang
  • Patent number: 10700673
    Abstract: Comparison circuit and delay cancellation method are provided. The circuit includes a control circuit, capacitors and a transconductance amplifier circuit, wherein the control unit is configured to receive an input signal and control the comparison circuit to be in different working stages; the capacitors are configured to store a DC offset voltage signal at an automatic zero calibration stage; store the input signal when the output signal is inverted at a measurement stage; and store an equivalent delay voltage signal at a delay sampling stage; the transconductance amplifier circuit is configured to store the DC offset voltage signal to the capacitors at the automatic zero calibration stage; compare voltage signals on positive and negative input terminals and generate an output signal at the measurement stage; and store the equivalent delay voltage signal to the capacitors at the delay sampling stage. An inherent delay of the comparison circuit may be cancelled.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: June 30, 2020
    Assignee: Wuxi Chipown Microelectronics Co., Ltd.
    Inventors: Leiyi Wang, Yutong Zou, Lixin Zhang