Abstract: An integrated circuit including a comparator having a first input to receive a reference voltage, a second input, and an output to provide an under-voltage indicator. Sense points are configured to provide a plurality of sense point voltages, each sense point providing a corresponding sense point voltage of the plurality of sense point voltages; and a minimum voltage tracking circuit configured to receive the plurality of sense point voltages and provide an output voltage which tracks whichever sense point voltage of the plurality of sense point voltages is currently a minimum sense point voltage. The comparator receives the output voltage at the second input and asserts the under-voltage indicator when the output voltage is below the reference voltage.

Abstract: An acoustic resonator filter includes: a series unit including at least one series acoustic resonator electrically connected, in series, between first and second ports configured to pass a radio frequency (RF) signal; a first shunt unit disposed on a first shunt connection path between the at least one series acoustic resonator and a ground, the first shunt unit including a plurality of shunt acoustic resonators connected to each other in series and having different resonance frequencies; and a second shunt unit disposed in a second shunt connection path between the at least one series acoustic resonator and the ground, the second shunt unit including at least one shunt acoustic resonator and having higher inductance than inductance of the first shunt unit.

Abstract: A speed-up circuit is configured to be provided between a power supply terminal and a gate of a semiconductor switching element. An impedance element is configured to be provided between a signal input terminal and a node, the node being between the speed-up circuit and the gate of the semiconductor switching element. In the speed-up circuit, a second field effect transistor is connected in series to a first field effect transistor and is configured to be connected to the gate of the semiconductor switching element. The impedance element has an impedance higher than an impedance of the speed-up circuit when both the first field effect transistor and the second field effect transistor are in an ON state.

Abstract: Embodiments provide a method for data storage and comparison, a storage comparison circuit device, and a semiconductor memory. The storage comparison circuit device includes a latch and a comparator. The latch is configured to latch inputted first input data and output first output data and second output data. The first output data are the same as the first input data, whereas the second output data are different from the first input data, wherein the first output data and the second output data are respectively inputted into the comparator. The comparator is configured to receive second input data, the first output data and the second output data, and to output a comparison result. By using modular structures of the latch and the comparator, device data can be simplified for the latch and the comparator, chip area can be reduced, calculation amount can be reduced, and efficiency of data comparison can be improved.

Abstract: The present disclosure relates to a high speed, differential input, single phase clock circuit. The circuit may include a cross-coupled PMOS connected with a cross-coupled NMOS via a pass gate. The circuit may further include a single-phase clock in communication with the cross-coupled PMOS and the cross-coupled NMOS. The circuit may also include a master and a slave each having an output node that charges and discharges to VDD or ground respectively, wherein there is no direct feedback from an output of the circuit to an input the circuit and there is no precharged state in the circuit.

Abstract: A power supply circuit includes a switchable match, including a high voltage bus connectable to a load, a low voltage bus connectable to the load such that the load is in series between the high voltage bus and the low voltage bus, at least two capacitors having a fixed value of capacitance selectively connectable between the high voltage bus and the low voltage bus and a plurality of solid state switches equal in number to the number of capacitors having a fixed value of capacitance connectable between the high voltage bus and the low voltage bus, each switch configured and arranged to selectively connect or disconnect one of the capacitors having a fixed value of capacitance selectively connectable between the high voltage bus and the low voltage bus into electrical communication between the high voltage bus and the low voltage bus, and a variable frequency power supply including a high voltage output connection, the high voltage connection connected to the high voltage bus.

Abstract: A circuit includes a field effect transistor (FET), a reference transistor having an output coupled to an output of the FET, an active bias circuit coupled to the reference transistor and configured to generate an input signal for the reference transistor in response to a change in drain current of the reference transistor due to carrier trapping and to apply the input signal to an input of the reference transistor, and a summing node coupled to an input of the FET and to the input of the reference transistor. The summing node adds the input signal to an input signal of the FET to compensate the carrier trapping effect.

Abstract: In various embodiments, a current measurement circuit measures an input current within an integrated circuit. The current measurement circuit includes an integration capacitor, an operational amplifier, a comparison capacitor, an inverter, and multiple switches. The current measurement circuit is coupled to a clocking circuit that, during operation, generates a two-phase clock having a frequency that is proportional to the input current. At least a portion of the switches are turned on during a first phase of the two-phase clock and are turned off during a second phase of the two-phase clock.

Abstract: The present disclosure relates to a recloser control that provides autosynchronization of a microgrid to an area electric power system (EPS). For example, a recloser control may include an output connector that is communicatively coupled to a recloser at a point of common coupling (PCC) between the area EPS and the microgrid. The recloser control may include a processor that acquires a first set of measurements indicating electrical characteristics of the area EPS and acquires a second set of measurements indicating electrical characteristics of the microgrid. The recloser control may send synchronization signals to one or more distributed energy resource (DER) controllers to synchronize one or more DERs to the area EPS based on the first set of measurements and the second set of measurements.

Abstract: A data receiving circuit is provided. The data receiving circuit includes a data input circuit, a latch circuit, and an equalizer. The data input circuit is configured to receive an input signal. The latch circuit is connected to the data input circuit and configured to output an output signal in response to the input signal. The equalizer is connected to the latch circuit and configured to provide a first voltage at a first node and a second voltage at a second node at an equalizing stage. The first voltage is different from the second voltage.

Abstract: A sample holding circuit includes a signal input terminal, a first sampling unit, a second sampling unit, and a holding unit. The signal input terminal receives a first reference voltage or a second reference voltage, the first sampling unit samples the first reference voltage when a first clock signal is triggered to obtain a first sampling voltage, the second sampling unit samples the second reference voltage when a second clock signal is triggered to obtain a second sampling voltage. The holding unit receives the first sampling voltage and the second sampling voltage when a third clock signal is triggered. The sample holding circuit effectively simplifies circuit structure and reduces the use of amplifiers, also improving the signal to noise ratio.

Abstract: Circuits and methods for maintaining loop stability and good load regulation in low loop gain LDO regulator circuits. Embodiments encompass LDO regulator circuits that include an offset error correction circuit that generates an opposing voltage VOFFSET as a function of load current to substantially cancel out variations in VOUT that would otherwise occur due to load regulation limitations of the LDO regulator circuits. Embodiments use VOFFSET to imbalance currents in differential paths in a last-stage LDO error-amplifier so that an offset is propagated to a pair of inputs to the error-amplifier, thereby altering the output voltage VOUT to a corrected value. Benefits include improved LDO load regulation even when feedback loop gain is low, the available of both digital and analog implementations, high LDO accuracy and less variation of the output voltage VOUT, and suitability for implementation in integrated circuits for applications such as high precision power supplies.

Abstract: The present disclosure relates to an electronic device comprising a pair of first transistors, each first transistor being coupled to a first node by a conduction terminal, a pair of second transistors, each second transistor being coupled to a second node by a conduction terminal, and a third transistor coupling the first and second nodes, the control terminal of the third transistor being coupled to the output of an operational amplifier, the operational amplifier being coupled, at its input, to the first node and to a node of application of a reference voltage.

Abstract: An electronic system device comprises a power generation device generating a power supply voltage, a substrate bias generation circuit connected to the power generation device, a memory circuit, a monitor circuit, and a capacitor connected to the substrate bias generation circuit via a switch. The substrate bias generation circuit generates a substrate bias voltage from the power supply voltage and supplies charges based on the substrate bias voltage to the capacitor while the switch is ON-state. While the switch is OFF-state, the capacitor stores the accumulated charges based on the substrate bias voltage. While the switch is ON-state, the substrate bias generation circuit adds based on the substrate bias voltage to charge that was held, and states the back bias voltage. The substrate bias generation circuit supplies the back bias voltage to memory circuit.

Abstract: In an example method of trimming a voltage reference circuit, the method includes: setting the circuit to a first temperature; trimming a first resistor (RDEGEN) of a differential amplifier stage of the circuit; and trimming a first resistor (R1) of a scaling amplifier stage of the circuit. The trimming equalizes current flow through the differential amplifier stage and the scaling amplifier stage. The method includes: trimming a second resistor (R2) of the scaling amplifier stage to set an output voltage of the circuit to a target voltage at the first temperature; setting the circuit to a second temperature; and trimming a second resistor (RPTAT) of the differential amplifier stage, a third resistor (R1PTAT) of the scaling amplifier stage, and a fourth resistor (R2PTAT) of the scaling amplifier stage to set the output voltage of the circuit to the target voltage at the second temperature.

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.

Abstract: The frequency detector includes a first impedance circuit and a second impedance circuit. The first impedance circuit has a first terminal for receiving an input signal, and a second terminal for outputting a divisional signal. The second impedance circuit has a first terminal coupled to the second terminal of the first impedance circuit, and a second terminal coupled to a first system voltage terminal. The frequency response of the first impedance circuit is different from a frequency response of the second impedance circuit. The resistance of the first impedance circuit, a resistance of the second impedance circuit, and the divisional signal change with a frequency of the input signal.

Abstract: A highly linear time amplifier with power supply rejection. In a reset stage, the threshold value of an over-threshold detector is used for resetting an output node of an amplifier, to eliminate the impact of power supply voltage changes on the threshold value of the threshold detector. A node capacitor unit is charged under the control of an input clock signal. After completion of charging, the node capacitor unit is discharged under the control of a synchronous clock signal. The time amplification gain only depends on the proportion of the charge and discharge current, and the charging and discharging time are completely linear in principle, which eliminates the nonlinearity of the traditional time amplifier, and reduces the negative impact of threshold change on system performance.

Abstract: According to one embodiment, a bus buffer circuit includes an input buffer circuit that receives an input signal, and outputs a non-inversion input signal and an inversion input signal, a voltage conversion circuit that operates by a second power supply, performs voltage conversion on the non-inversion input signal and the inversion input signal input thereto, and outputs the signals as a voltage-converted non-inversion output signal and a voltage-converted inversion output signal, an output retaining circuit that retains the voltage-converted non-inversion output signal and the voltage-converted inversion output signal at a same potential level when an output enable signal is in a disable state, a determinator that determines whether these signals are at a same potential level, a three-state output buffer circuit that outputs the voltage-converted non-inversion output signal or the voltage-converted inversion output signal from an output terminal, and an output controller that sets the three-state output buf

Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.