Patents Examined by Long Pham
  • Patent number: 8035126
    Abstract: A one-transistor static random access memory (1T SRAM) device and circuit implementations are disclosed. The 1T SRAM device includes a planar field effect transistor (FET) on the surface of the cell and a vertical PNPN device integrated to one side of the FET. A base of the PNP of the PNPN device is electrically common to the emitter/collector of the FET and a base of the NPN of the PNPN device is electrically common to the channel region of the FET. The anode pin of the PNPN device may be used as a word line or a bit line. A method of forming the 1T SRAM device is also disclosed.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: October 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Phung T. Nguyen, Robert C. Wong
  • Patent number: 8030718
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: October 4, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Tsung Huang, Shyh-Horng Yang, Yuri Masuoka, Ken-Ichi Goto
  • Patent number: 8030107
    Abstract: An electro-luminescent device includes a transparent substrate, a black matrix on the transparent substrate defining a plurality of spaces, a plurality of color representing layers each arranged in respective ones of the spaces, an overcoat layer on the black matrix and the color representing layers, a plurality of first electrodes disposed on the overcoat layer in a first direction with respect to the color representing layers, a phosphor layer formed on the plurality of first electrodes, an insulating film on the phosphor layer, and a plurality of second electrodes disposed on the insulating film in a second direction perpendicular to the first direction.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: October 4, 2011
    Assignee: LG Display Co., Ltd.
    Inventors: In Jae Chung, Gee Sung Chae
  • Patent number: 8030688
    Abstract: A method for fabricating a semiconductor device which protects the ohmic metal contacts and the channel of the device during subsequent high temperature processing steps is explained. An encapsulation layer is used to cover the channel and ohmic metal contacts. The present invention provides a substrate on which a plurality of semiconductor layers are deposited. The semiconductor layers act as the channel of the device. The semiconductor layers are covered with an encapsulation layer. A portion of the encapsulation layer and the plurality of semiconductor layers are removed, wherein ohmic metal contacts are deposited. The ohmic metal contacts are then annealed to help reduce their resistance. The encapsulation layer ensures that the ohmic metal contacts do not migrate during the annealing step and that the channel is not harmed by the high temperatures needed during the annealing step.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: October 4, 2011
    Assignee: HRL Laboratories, LLC
    Inventors: Tahir Hussain, Miroslav Micovic, Paul Hashimoto, Gary Peng, Ara K. Kurdoghlian
  • Patent number: 8030715
    Abstract: A semiconductor device with a gate having a bulbous area and a flattened area underneath the bulbous are is presented. The semiconductor device includes a semiconductor substrate, an isolation layer, a gate insulation layer, and gates. The semiconductor substrate has recess parts that have first grooves which have bulbous-shaped profiles and second vertically flattened profile grooves which extend downward from the first grooves. The gates are formed in the recess parts in which the gate insulation layer is double layered in the bulbous profile areas and is single layered in the flattened profile areas.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: October 4, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung Gil Chun
  • Patent number: 8027486
    Abstract: Disclosed herein are detectors of audio ringing feedback, that is decaying feedback with a gain of less than one, those detectors utilizing a repeated gain measurement that applied to a range of gain values characteristic of ringing-type feedback. Those gain measurements, while in the range, increase a probability measurement of feedback. When the probability of feedback reaches a threshold, a detection of feedback is made and feedback countermeasures, such as the application of a notch filter, may be applied. Optionally, the audio gain around likely frequencies of feedback may be enhanced for a time to increase the resolution of identification of a feedback frequency, which may be identified through an interpolative method. Repeated gain measurements may also identify building-type feedback. A ringing detector may include more than one range of detection, for example for building, strong-ringing and weak-ringing feedback.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: September 27, 2011
    Assignee: Clearone Communications, Inc.
    Inventors: Ashutosh Pandey, David Lambert
  • Patent number: 8026890
    Abstract: According to one embodiment of the present invention, a flat display device which makes drive voltage polarity of pixels of adjacent lines reversed polarity, while drives to reverse drive voltage polarity of the same line on a frame-by-frame basis, has common voltage generation circuit for supplying a common voltage signal to a facing electrode of the flat display device and a control circuit for generating a common voltage control signal supplied to the common voltage generation circuit. The control circuit obtains a control signal for generating common voltage whose average DC potential does not vary, by using a horizontal synchronization timing signal, a vertical synchronization timing signal, and a clock signal. In order to obtain the control signal, the device has an (fh/2) signal generation circuit, an (fv/2) signal generation circuit, an (fh×n) signal generation circuit, an multiplication circuit, a selection control circuit, and a selection circuit.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: September 27, 2011
    Assignee: Toshiba Matsushita Display Technology Co. Ltd
    Inventor: Kimio Anai
  • Patent number: 8026514
    Abstract: The present invention relates to a new diamine derivative, and an organic electronic device using the same. The diamine derivative according to the present invention can serve as a hole injecting, hole transporting, electron injecting, electron transporting, or light emitting material in an organic electronic device including an organic light emitting device. Particularly, it can serve as a light emitting dopant as used alone, in particular, a blue light emitting dopant. The organic electronic device according to the present invention exhibits excellent characteristics in terms of efficiency, drive voltage, life time, and stability.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: September 27, 2011
    Assignee: LG Chem, Ltd.
    Inventors: Hye-Young Jang, Kong-Kyeom Kim, Jae-Chol Lee, Ji-Eun Kim, Seong-So Kim, Jin-Kyoon Park, Tae-Yoon Park, Eun-Ju Kim, Wook-Dong Cho, Byung-Sun Jeon, Jae-Soon Bae
  • Patent number: 8022459
    Abstract: The invention is directed to a device for regulating the flow of electric current with high dielectric constant gate insulating layer and a source and/or drain forming a Schottky contact or Schottky-like region with a substrate and its fabrication method. In one aspect, the gate insulating layer has a dielectric constant greater than the dielectric constant of silicon. In another aspect, the current regulating device may be a MOSFET device, optionally a planar P-type or N-type MOSFET, having any orientation. In another aspect, the source and/or drain may consist partially or fully of a silicide.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: September 20, 2011
    Assignee: Avolare 2, LLC
    Inventors: John P. Snyder, John M. Larson
  • Patent number: 8022436
    Abstract: A light emitting diode includes a substrate, a compound semiconductor layer including a light emitting layer formed on the substrate, a first electrode formed on an upper surface of the compound semiconductor layer, and a second electrode formed on the substrate or a semiconductor layer which is exposed by removing at least a portion of the compound semiconductor layer. The first electrode includes a wiring electrode provided on the compound semiconductor layer in contact therewith, an ohmic electrode provided on the compound semiconductor layer in contact therewith, a translucent electrode formed over the compound semiconductor layer to cover the wiring electrode and the ohmic electrode, and a bonding pad electrode connected to the wiring electrode, at least a portion of the bonding pad electrode being exposed from an opening of the translucent electrode to the exterior.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: September 20, 2011
    Assignee: Showa Denko K.K.
    Inventors: Ryouichi Takeuchi, Kyousuke Masuya
  • Patent number: 8022550
    Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: September 20, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
  • Patent number: 8018421
    Abstract: A gate driver of a liquid crystal display includes classes of driving circuits coupled to each other for outputting gate pulses. At least one class of driving circuits includes a shift register and a switch. The shift register outputs the gate pulse corresponding to the class of driving circuit according to the gate pulse outputted by a former class of driving circuits. The switch controls the enable of the shift register according to the gate pulse outputted by the former class of driving circuit and the gate pulse outputted by the class of driving circuit.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: September 13, 2011
    Assignee: Himax Technologies Limited
    Inventor: Mao-Hsiung Kuo
  • Patent number: 8017502
    Abstract: A wafer system is provided including providing a wafer having a topside and a backside, forming a partial cut from the topside of the wafer within a wafer rim and thinning the wafer from the backside for exposing the partial cut at the backside within the wafer rim.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: September 13, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Taewoo Lee, Sang-Ho Lee
  • Patent number: 8013328
    Abstract: An active matrix organic optical device comprising a plurality of organic thin film transistors and a plurality of pixels disposed on a common substrate, wherein a common bank layer is provided for the organic thin film transistors and the pixels, the common bank layer defining a plurality of wells, wherein some of the wells contain the organic semiconducting material of the organic thin film transistors therein and others of the wells contain organic optically active material of the pixels therein.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: September 6, 2011
    Assignee: Cambridge Display Technology Limited
    Inventors: Jeremy Burroughes, Mark Bale, Mark Garbett, Jonathan Halls
  • Patent number: 8013825
    Abstract: In a method for addressing rows and columns in a liquid crystal display, each phase for addressing rows and columns in the display includes precharging pixels of the display before a row write, to apply a precharge voltage to all pixels. Depending on the selected black or white precharge level, the light box is either switched on permanently, or is switched on during each addressing phase immediately after the precharge or immediately after the row write. The display brightness is thus improved. The display may be of sequential color type.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: September 6, 2011
    Assignee: Thales
    Inventors: Hugues Lebrun, Thierry Kretz
  • Patent number: 8013330
    Abstract: Disclosed are a compound for an organic electroluminescent device (organic EL device) which is improved in luminous efficiency, fully secured of driving stability, and of simple constitution and an organic EL device using said compound. The compound for an organic EL device has two indolocarbazole skeletons each of which is bonded to an aromatic group or two skeletons similar thereto. The organic EL device comprises a light-emitting layer disposed between an anode and a cathode piled one upon another on a substrate and said light-emitting layer comprises a phosphorescent dopant and the aforementioned compound for an organic EL device as a host material.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: September 6, 2011
    Assignee: Nippon Steel Chemical Co., Ltd
    Inventors: Masaki Komori, Toshihiro Yamamoto, Takahiro Kai, Katsuhide Noguchi, Hiroshi Miyazaki
  • Patent number: 8012835
    Abstract: A high voltage operating field effect transistor has a source region and a drain region spaced apart from each other in a surface of a substrate. The source region is operative to receive at least one of a signal electric potential and a signal current. A semiconductor channel formation region is disposed in the surface of the substrate between the source region and the drain region. A gate region is disposed above the channel formation region and is operative to receive a bias electric potential having an absolute value equal to or larger than a first constant electric potential which changes according to an increase or decrease in a drain electric potential. A gate insulating film region is disposed between the channel formation region and the gate region.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: September 6, 2011
    Assignees: Seiko Instruments Inc.
    Inventors: Yutaka Hayashi, Hisashi Hasegawa, Yoshifumi Yoshida, Jun Osanai
  • Patent number: 8012870
    Abstract: In a wiring structure between steps in which a step portion is covered by an insulating slope formed by providing and drying droplets of an insulating ink in which an insulating material is dispersed in a dispersion medium and a wiring line formed by drying and firing provided droplets of a conductive ink in which a conductive material is dispersed in a dispersion medium is laid out between the steps and passes on a top surface of the insulating slope, the structure includes a liquid repellent layer formed of a liquid repellent material repelling the dispersion medium in the insulating ink, and a plurality of dot lines including a plurality of dots that is formed by hardening arranged droplets of a resin ink including a resin material. In the structure, the liquid repellent layer covers a surface including the step portion where the wiring line to be laid out.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: September 6, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Noboru Uehara
  • Patent number: 8008657
    Abstract: Disclosed are an organic electroluminescent device (organic EL device) which is improved in luminous efficiency, fully secured of driving stability, and of simple constitution and a compound useful for the fabrication of said organic EL device. The compound for the organic EL device has an indolocarbazole structure or a structure similar thereto in the molecule wherein an aromatic group is bonded to the nitrogen atom in the indolocarbazole. The organic EL device has a light-emitting layer disposed between an anode and a cathode piled one upon another on a substrate and said light-emitting layer comprises a phosphorescent dopant and the aforementioned compound for an organic electroluminescent device as a host material.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: August 30, 2011
    Assignee: Nippon Steel Chemical Co., Ltd.
    Inventors: Takahiro Kai, Masaki Komori, Toshihiro Yamamoto, Katsuhide Noguchi, Hiroshi Miyazaki
  • Patent number: 8003420
    Abstract: According to one feature of the invention, a region of an insulating film surface at least overlapped with a part of a gate electrode or wiring is coated with an organic agent; a fluid in which conductive fine particles are dispersed in an organic solvent is discharged by a droplet discharging method in the insulating film surface ranging from a region where the organic agent is coated and left to a region where the organic agent is not coated. The organic agent is coated to improve wettability of the fluid in the insulating film surface, and one of each ends of the source electrode and the drain electrode adjacent to each other by interposing the curve therebetween is formed by being curved in a concave and the other end is formed by being curved in a convex.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: August 23, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shinji Maekawa