Abstract: The FPGA array in the Simulation system is provided on the motherboard through a particular board interconnect structure to provide easy expandability and maximize packaging density with a single PCB design. Each chip may have up to eight sets of interconnections, where the interconnections are arranged according to adjacent direct-neighbor interconnects (i.e., N[73:0], S[73:0], W[73:0], E[73:0]), and one-hope neighbor interconnects (i.e., NH[27:0], SH[27:0], XH[36:0], XH[72:37]), excluding the local bus connections, within a single board and across different boards. Each chip is capable of being interconnected directly to adjacent neighbor chips, or in one hop to a non-adjacent chip located above, below, left, and right. In the X direction (east-west), the array is connected in a torus. In the Y direction (north-south), the array is connected in a column.

Abstract: A real-time data management system which uses data generated at different rates, by multiple heterogeneous incompatible data sources. In one embodiment, the invention is as an airport surface traffic data management system (traffic adviser) that electronically interconnects air traffic control, airline, and airport operations user communities to facilitate information sharing and improve taxi queuing. The system uses an expert system to fuse data from a variety of airline, airport operations, ramp control, and air traffic control sources, in order to establish, predict, and update reference data values for every aircraft surface operation.

Abstract: A method and system for co-verifying a hardware simulation of a field-programmable-system-level integrated circuit (FPSLIC) and a software simulation of the field-programmable-system-level integrated circuit. A FPSLIC device is simulated in hardware, and a simulator-port layout of the FPSLIC device is generated. In software, the method separately simulates, with an instruction-set simulator, the FPSLIC device, and outputs register contents from the instruction-set software. The contents from the simulator-port layout are verified with the register contents. Additionally, the method may further include outputting peripheral contents from the instruction-set simulator, and verifying contents from the simulator-port layout with the peripheral contents. UART contents also may be outputted from the instruction-set simulator, and verified with contents from the simulator-port layout with the UART contents.

Abstract: An improvement to split-architecture audio codecs such as those defined by the Audio Codec '97 specification (AC '97) includes a simulated analog-to-digital (A/D) digitization of the PC beep signal from a personal computer (PC). A PC beep simulated A/D digitization circuit simulates the A/D conversion of the PC beep signal. The PC beep simulated A/D digitization circuit eliminates the need for a pre-amplifier, and reduces the design complexity and power consumption otherwise necessary for an A/D converter, by outputting either of two simulated A/D converter values corresponding respectively to a conversion of the HIGH and LOW logic levels of the PC beep signal. The simulated A/D converter output signal from the PC beep simulated digitization circuit is subsequently scaled and summed with the digital signals from other audio sources, and output from the audio codec.

Abstract: A dimensioning system is provided for a computer generated model of a sheet metal part including a plurality of entities. The dimensioning system comprises a model display, an indicator, a selector, a dimension defining system, and a dimension display. The model display displays a representation of the model on a display screen. The indicator indicates to a user candidate entities of the model, in response to user events, that may be selected. The selector selects two entities of the model, based on an indicated candidate entity. The dimension defining system defines each dimension associated with the selected entities of the model. The dimension display displays dimension information on the display screen based on the defined dimension. A repositioning system is also provided for a computer generated model of a sheet metal part represented on a display screen. The sheet metal part has associated dimensions displayed along with the sheet metal part on the display screen.

Abstract: The method and system of discretisation according to the present invention addresses the problems of the different types of prior art grids. In particular, a problem for which a solution is found is that of the rigidity of the spatial distribution of the cells in a structured grid, implying undesired local thickening of cells, thus causing considerable waste in calculation time and memory. A method consistent with the present invention creates a semistructured grid. Further, a numerical solver needs to be adapted to handle the semistructured grid.

Abstract: A system and method for conducting a multi-person, interactive auction, in a variety of formats, without using a human auctioneer to conduct the auction. The system is preferably implemented in software. The system allows a group of bidders to interactively place bids over a computer or communications network. Those bids are recorded by the system and the bidders are updated with the current auction status information. When appropriate, the system closes the auction from further bidding and notifies the winning bidders and losers as to the auction outcome.

Abstract: A co-simulation design system that runs on a host computer system is described that includes a hardware simulator and a processor simulator coupled via a interface mechanism. The execution of a user program is simulated by executing an analyzed version of the user program on the host computer system. The analysis adds timing information to the user program so that the processor simulator provides accurate timing information whenever the processor simulator interacts with the hardware simulator.

Abstract: The present invention is directed to a system for for automated interface generation for computer programs operating in different environments. The system comprises a utility which imports a CICS COBOL transaction source file, parses the communication area of the CICS file, and generates modelling information. The modelling information represents the nature and structure of data in the CICS transaction source file, and is written to a persistent data store. The utility uses the information in the persistent data store to generate an application programming interface. The application programming interface takes the data values from the other language and translates them to a formatted CICS COBOL communications area. This format is derived from the definition of the CICS communications area contained in the imported CICS program. After the translation runs, the resulting CICS COBOL communications area is translated back to the data values of the other language.

Abstract: A method and system are disclosed that utilize the expressiveness of hardware description languages for incrementally compiling instrumentation logic into a simulation model of a digital circuit design. According to the present invention, a simulation model that includes a design entity file of a digital circuit design is generated. Next, an instrumentation entity file is associated with the design entity file, thereby producing an instrumented design entity file. Finally, and during the process of compiling the simulation model, for the instrumented design entity file: searching for a consistent and previously compiled version of said instrumented design entity file. In response to finding a consistent and previously compiled version, loading the consistent and previously compiled version into the simulation model. In response to finding no consistent and previously compiled version, loading and compiling the instrumented design entity file.

Abstract: An apparatus (or a multitude of apparati) for modeling the solution (or the results) of a set of differential equations including single differential equations comprising fluid circuits having reservoir units (RUs) of various shapes to store and release fluids and friction units (FUs) to resist (in a linear or nonlinear manner) the flow of fluids. The fluid circuits can be arranged in series, parallel, loop or combinations thereof forming a system defined by a set of linear, nonlinear or combination thereof of differential equations. The system is under various forcing function where the forcing functions can comprise continuous, discontinuous, constant, variable, periodic flow and potential heads applied at least to one reservoir units (RU). The inputs results in outputs in all reservoir units (RUs) and friction units (FUs) and the outputs are monitored and are solutions to the set of differential equations defining the system.

Abstract: A simulator apparatus for a combined simulation of electromagnetic wave analysis and circuit analysis, which is configured to produce stable solutions with a smaller amount of processing loads. An electromagnetic wave analyzer calculates magnetic field at a simulation time tem01 and then electric field at another simulation time tem02 thereby performing a transient analysis of electromagnetic waves. A circuit analyzer solves the given circuit equation at still another simulation time tcs that is incremented by a variable time step size &Dgr;tcs determined in accordance with the circumstances. A current source data transfer unit compares tem01 and tcs, and if their difference falls below a time difference threshold &lgr;1, it calculates current source data for the equivalent circuit, based on the magnetic field obtained by the electromagnetic wave analyzer. The current source data transfer unit then transfers the resultant current source data to the circuit analyzer.

Abstract: Methods and apparatus for modeling behavior. A computer model includes an agent having one or more beliefs, a world model, and facts. Behavior is modeled by frames including workframes modeling a time-consuming portions of an activity or thoughtframes modeling non-time-consuming portions of an activity or information processing. Detectables model acquisition of, and response to, information during a defined portion of an activity. A detectable tests facts to form beliefs of the agent, which can affect continued performance of the activity. The model is run by selecting for each time one of the frames to be the working frame; maintaining a context of active frames representing activities that are underway at any time; performing the working frame until it completes or another frame is selected to be performed in its place.

Abstract: A method, apparatus and article of manufacture for mirroring a part model within a computer aided design computer system. A physical body, which is not directly accessible to the user is used for boundary representation of the non-mirrored part model, and a special mirror transformed instance of the physical body, called the logical body, is presented to the user. The logical body is a mirrored boundary representations of the same part model, and is not persistent to conserve computer resources. The invention uses face, edge, and vertex mapping to communicate between the two bodies, and uses matrix multiplication to perform the mirroring transformation.

Abstract: A method and system are disclosed that utilize the expressiveness of hardware description languages for automatically adjusting counting rates of instrumentation within a simulation model of a digital circuit design, during simulation of said digital circuit design. According to the present invention a design entity that will be incorporated into a simulation model of a digital circuit design is described utilizing a hardware description language. The design entity operates, during simulation, in conformity with a design cycle that consists of a multiple of a simulator cycle. Next, an instrumentation entity is described utilizing the same hardware description language. The description of the instrumentation entity contains logic to detect occurrences of a count event that occurs in conformity with the design cycle during simulation.

Abstract: A method and system are disclosed that utilize the expressiveness of hardware description languages for providing comprehensive runtime monitoring during hardware accelerated simulation of a digital circuit design. According to the present invention a design entity forming part of a digital circuit design that will be translated and assembled into a simulation executable model, is described utilizing a hardware description language. Next, an instrumentation entity designed to send a failure signal in response to detecting an occurrence of a failure event within the simulation executable model is described utilizing the same hardware description language. Thereafter, a simulation test is initiated on the simulation executable model utilizing a hardware simulator. Finally, during the simulation test, and in response to receiving a failure signal from the instrumentation entity, the simulation test is terminated such that the failure event may be efficiently identified and diagnosed.

Abstract: A method and system are disclosed that utilize the expressiveness of hardware description languages for selectively disabling instrumentation during simulation of a digital circuit design. According to the present invention, an instrumentation entity, described utilizing a hardware description language to include an output signal to indicate an occurrence of an event during simulation, is implemented into a simulation model of a digital circuit design. Next, the output signal is associated with a unique output storage element. Finally, a disable mechanism uniquely associated with said output signal is provided, such that the output signal may be selectively masked by disabling the storage element during simulation testing of the digital circuit design.

Abstract: A method and system are disclosed that utilize the expressiveness of hardware description languages for efficiently and comprehensively monitoring performance characteristics of a digital circuit design during simulation. According to the present invention, a design entity that is part of a digital circuit design is first described utilizing a hardware description language. Next, an instrumentation entity is described utilizing the same hardware description language. Thereafter, the design entity is instantiated in at least one instance within a simulation model of a digital circuit design. Finally, the instrumentation entity is associated with the design entity utilizing a non-conventional call, such that the instrumentation entity may be utilized to monitor each instantiation of the design entity within the simulation model without the instrumentation entity becoming incorporated into the digital circuit design.

Abstract: Children, particularly those younger than 4 years, frequently place foreign objects such as toys and small parts of consumer products in their mouths, nasal cavities and ear canals. These actions not infrequently lead to injury or death. To asses the risk of injury or death in children at the critical stages of child development, accurate computerized and physical models of anatomical areas including the oral cavity, orbit, ear canal and nasal passages that are most often severely injured by foreign body impaction are created. These computer and physical anatomical models are used in combination with computer and physical models of products to assess the possible hazards inherent in a product design and to communicate the risks associated with product design to manufacturers and marketing groups.

Abstract: Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that wire routine be done correctly to avoid any congestion of wires. Congestion of wires can be determined by actually routing of the wires to connect the cells; however, the routing process is computationally expensive. For determination of congestion, the only required information are the location of the connections, or edges, to connect the pins of the IC. The present invention discloses a method to quickly provide a good estimate of the location of the edges, or connections for an IC. The present invention provides for a method to determine all the edges and superedges (bounding boxes, or areas where an edge will take space) of an IC without requiring to determine the actual routing of the wires of an IC.