Abstract: Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that placement of the cell and the wire routine be done correctly to avoid any congestion of wires. The present invention discloses method and apparatus to optimize the cell density of the segments of columns on the IC. To optimize the segment or column density, the present columns densities are calculated, and the desired densities are determined. Then, the amount and the location of the of cell overload is found. The cells of the overloaded columns are spread out the neighboring columns. The reassignment of the cells are performed to minimize the distance, therefore the affect, of the relocation.

Abstract: A method is provided for automatically enhancing verification of a design under test by using model checking on the state transitions captured during simulation. The enhanced verification is due to the fact that even though to all of the individual transitions captured were exercised during simulation, not all possible sequences of those transitions were necessarily exercised during the simulation, and the unexercised sequences may hide "bugs". The non-deterministic and exhaustive nature of the model checker ensures that all possible sequences comprising the captured state transitions are exercised. The methodology consists of utilizing the state transitions, and the inputs causing those state transitions as observed during simulation, to define legitimate input values that can be applied, nondeterministically and exhaustively, by the model checker to the design under test.

Abstract: A method and apparatus for calculating parasitic capacitance between conductors of an integrated circuit. A physical structure which includes a conductive wire within an integrated circuit is considered. Limiting cases of the structure are then selected to simplify the derivation of an accurate parasitic capacitance expression. The limiting cases are simplified and structural variables may be combined, so as to reduce the data set necessary to extract or interpolate an expression for calculating the parasitic capacitance for each of the limiting cases. A second set of limiting cases, representing simplified physical structures, is then chosen. Again, simplification techniques are used to simplify each of the original limiting cases. The is simplified limiting case expressions are combined to derive a more generalized relationship where capacitance is a function of a reduced number of parameters.

Abstract: An apparatus for simulating a logic circuit is disclosed comprising a first plurality of logic block circuits for simulating portions of the logic circuit the logic block circuits having a predetermined number of inputs and outputs; at least one routing logic block for routing signals between the logic block circuits; each of the logic block circuits further including: a first series of output scan chain units for capturing and storing each of the signal outputs of a corresponding the logic block circuit; and a second series of input scan chain units for storing and inputting a signal to each of the logic block inputs; each of the scan chain units being further interconnected to the routing logic block for the storing of the input signals and the output signals to and from the routing logic block.

Abstract: A method, apparatus, and article of manufacture for performing timing analysis on an integrated circuit, which run a high level chip timing tool with initial RC delays for all nets of the integrated circuit; determine a list of time-critical nets from a timing report and obtain a full RC coupling network for each time-critical net; run a detailed circuit simulator on the full RC coupling network for each time-critical net to obtain actual RC delays for each time-critical net; determine a delta time for each time-critical net, based on a difference between the initial RC delay and the corresponding actual RC delay for each time-critical net; and rerun the high level chip timing tool, including the delta time for each time-critical net to obtain a timing analysis of the integrated circuit which accounts for signal to signal noise.

Abstract: The present invention provides an apparatus for evaluating the performance of an MP system which is configured, to simulate the MP system highly accurately and speedily, in such a way as to comprise: a trace-data sampling part for sampling execution-trace data for each processor; a trace-data conversion part for converting execution-trace data sampled for each processor by the trace-data sampling part, thus estimating substantial processing time in the processor; and a simulation part for performing simulation of the MP system based on the processing time estimated for each processor by the trace-data conversion part, in order to evaluate the performance of the MP system.

Abstract: A method and apparatus for generating a library for use in a logic simulator. The library includes information on a plurality of cells whose functions are expressed in accordance with a truth table model by combining patterns of input signals and output signals. Information on each cell is input to the logic simulator. It is determined if an input signal to each cell includes an edge signal indicative of rising or falling of that input signal. When the input signal includes the edge signal, the pattern is selected. The selected pattern is then separated from the truth table model of the cell and is developed into two patterns. The developed two patterns include input signals having different levels according to the edge signal. The remaining and developed patterns are thereafter combined to form a new truth table model to be used in the simulation. When the truth table model has reference to a self-output value, a new table is formed that includes a virtual memory.

Abstract: An emulation apparatus and method in which software containing both instructions and data from a given computer of a given architecture is converted into software to be executed on another computer with a different type of architecture. This is accomplished by a target source software holding section holding the source code to be converted. Then a program data conversion processing section sequentially converts the software program from a starting address to an address in which a branch instruction is contained. The main software is held by a main software holding section. A conversion state registering section registers identification data showing if the program data to be converted is already converted for each corresponding address.

Abstract: A simulator and its operation, for simulating electromagnetic behaviour of an IC (integrated circuit) of thin-film passive circuit components, uses a simple equivalent circuit model to minimise computer processing time while retaining good model accuracy in spite of the energy losses and different film thicknesses, conductivities and dielectric properties which occur in a passive integration IC.

Abstract: A pre-production, prototype multi-chip module adapted for preliminary performance timing and functional tests includes a plurality of chips attached to a substrate. Multiple nets are embedded within the substrate connecting the chips. A layer over the substrate encapsulates the chips. Production input/output pins on the substrate are connected to the chips. An area on the upper surface of the module is not covered by the encapsulating layer, which contains upper pads adapted for connection of a second module containing spare circuits to the substrate, wherein the upper pads are connected to the at least one net. Some of the upper pads have connections to each other near the surface of the encapsulating layer, wherein the connections are adapted to be severed for connecting a second module containing spare circuits to one or more of the chips.

Abstract: A method and an apparatus for coupling the results of behavioral synthesis with those of logic synthesis. It uses a timing verifier to precalculate the timing characteristics of a circuit for use by behavioral synthesis. Timing for control chaining is included in the precalculated timing characteristics. Once behavioral synthesis is complete, logic synthesis is informed of timing constraints introduced by behavioral synthesis.

Abstract: The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present.

Abstract: A method for the automatic scaling of radio receiver characteristics. Receiver designs are subject to change based upon the parameters of transmitters and the desired characteristics of communications links in a communications system. The method of the present invention involves automatically scaling the characteristics of a receiver based upon the transmitter proposed and the desired characteristics of a communications link. Auto-scaling calculates the bandwidth necessary for the receiver based upon the transmitter proposed. Information concerning the modulation type and the scaling factor associated with each modulation type are stored in a database for access by the system. Once transmitter characteristics are known, receiver characteristics are automatically calculated. The system allows for multiple designs to be created so that analysts can select the optimal design for the mission.

Abstract: Multiple processor circuit simulator comprising a debugger interface, a synchronizer, a RISC processor simulator, a vector processor simulator, a shared memory, a co-processor interface module and an events module. The multiple processor simulator tightly couples the RISC processor simulator and vector processor simulator into a single executable process and a single address space. The synchronizer interleaves simulation of instruction execution between multiple processor simulators. The synchronizer determines which processor simulator to execute based on a furthest-behind clocking scheme. The clocking scheme is implemented by comparing the values held in clock simulators corresponding to the processor simulators.

Abstract: The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present.

Abstract: A micropower impulse radar is used to take measurements, such as those needed to establish room size and the dimensions and location of objects within the walls of a room. A computer controls the scanning of the radar and the collection of datapoints. A global positioning satellite (GPS) unit locates the precise portion of the radar and another unit loads a fixed referenced location to which all measurements from different rooms are baselined. By collecting points and referencing them to a common point or wireframe representation of a building can be developed from which "as built" architectural plans can be produced.

Abstract: A furniture specification system, designed for relatively large scale office furniture projects, having three basic components: 1) means for generating a furniture specification which contains data specifying a plurality of the available furniture products; 2) means for generating a visual display of the furniture products specified by the furniture specification on a display device; and 3) means for generating a cost specification based upon the furniture specification. Since both the visual display of the furniture products and the cost specification are generated from the same furniture specification, the possibility of discrepancies between the visual display and the cost specification is eliminated. The means for generating the furniture specification allows the user to add or delete individual products and to add product clusters to the furniture specification.

Abstract: A method and apparatus for tracing any node in an emulator, including hidden nodes of a circuit design, includes maintaining a correspondence between physically observable nodes and hidden nodes of the circuit design being emulated. The correspondence identifies how values of the hidden nodes are to be determined based on corresponding ones of the physically observable nodes. The value of a hidden node is determined by obtaining the values of the corresponding physically observable nodes and identifying the value of the hidden node based on the correspondence between the corresponding physically observable nodes and the hidden node.

Abstract: A method of automatic and user intuitive cataloging of removable media on a computer. The method does not require the user to launch an application to catalog because it operates within the existing system software and does not require a user to learn to operate a separate cataloging program. This applies to cataloging as well as searching entries. The method presents the data in the catalog in the same way that actual files on the computers hard disk or start up volume are presented. The method includes modifying and/or creating pointer files so that when activated it can remember where the original file is located, even the file is on a volume that is not accessible to the computer when the pointer file is activated. The pointer file created by this method can be resolved when accessed through the operating system interface or from within an application, just like actual files.

Abstract: An interactive graphical software tool is provided that can be used to report the configuration data (i.e., the state of the various configuration bits) in a programmed device as well as to probe and stimulate circuits in the programmed device. A graphical or textual representation of the configuration data can be displayed. When used with a programmable device having addressable flip-flops, such as a member of the Xilinx XC6200 family, one embodiment of the invention can change the state of any addressable flip-flop in the configured device. The graphical tool of the invention is preferably implemented using a high level programming language such as Java and features a graphical point and click user interface, remote access to hardware, and symbolic debug capability. According to another aspect of the invention, data can be written into a programmable device using an interactive software tool and a hardware device designed to interface with the programmable device.