Abstract: A semiconductor package substrate with embedded chip and a fabrication method thereof are provided. A first insulating layer is applied on a metallic board, and formed with at least one opening for exposing a portion of the metallic board. At least one semiconductor chip is mounted on the exposed portion of the metallic board. A support plate is mounted on the first insulating layer, and formed with a through cavity at a position corresponding to the opening of the first insulating layer, for receiving the chip in the through cavity. A second insulating layer is applied on the chip and the support plate. Insulating materials of the insulating layers fill a gap between the chip and the support plate. A circuit layer is formed on the second insulating layer, wherein the circuit layer is electrically connected to the chip by conductive structures formed in the second insulating layer.

Abstract: A mechanical structure is disposed in a chamber, at least a portion of which is defined by the encapsulation structure. A first method provides a channel cap having at least one preform portion disposed over or in at least a portion of an anti-stiction channel to seal the anti-stiction channel, at least in part. A second method provides a channel cap having at least one portion disposed over or in at least a portion of an anti-stiction channel to seal the anti-stiction channel, at least in part. The at least one portion is fabricated apart from the electromechanical device and thereafter affixed to the electromechanical device. A third method provides a channel cap having at least one portion disposed over or in at least a portion of the anti-stiction channel to seal an anti-stiction channel, at least in part. The at least one portion may comprise a wire ball, a stud, metal foil or a solder preform. A device includes a substrate, an encapsulation structure and a mechanical structure.

Abstract: The invention provides a method and device for building one or more passive components into a chip scale package. The method includes the steps of selecting a passive component having a terminal pitch that is a multiple of the package ball pitch of a chip scale package and mounting the selected passive component terminals to ball sites of the package. A preferred embodiment of the invention uses a single metal layer polyamide tape as the substrate of the package. Additional preferred embodiments of the invention are disclosed in which the terminal pitch multiple of the package ball pitch is one or two. Devices corresponding to the disclosed methods are also disclosed.

Abstract: The invention relates to a substrate with slot. The substrate of the invention comprises an active surface and a plurality of metal plates. The metal plates are formed on the active surface. Each metal plate has a first surface and a second surface. The first surface is connected to the active surface. At least one metal plate has at least one slot formed on the second surface. Therefore, according to the substrate with slot of the invention, a resin for connecting a chip and the metal plates can entirely seal sides and corners of the chip so as to prevent water or dust from entering the chip and protect the chip.

Abstract: A chip package structure includes a substrate, a chip, a first B-stage adhesive, bonding wires, a heat sink and a molding compound. The substrate comprises a first surface, a second surface and a through hole. The chip is arranged on the first surface of the substrate and electrically connected thereto while the through hole of the substrate exposes a portion of the chip. The first B-stage adhesive is arranged between the chip and the first surface of the substrate, and the chip is attached to the substrate through the first B-stage adhesive. The bonding wires are connected between the chip exposed by the through hole and second surface of the substrate. The heat sink is arranged on the first surface of the substrate, covering the chip. The molding compound is arranged on the second surface of the substrate, covering a portion of the substrate and bonding wires.

Abstract: A method of packaging a semiconductor die includes the steps of providing a flange (110), coupling one or more active die (341) to the flange with a lead-free die attach material (350), staking a leadframe (120) to the flange after coupling the one or more active die to the flange, electrically interconnecting the one or more active die and the leadframe with an interconnect structure (470), and applying a plastic material (130) over the flange, the one or more active die, the leadframe, and the interconnect structure.

Abstract: The present invention is a method of fabricating a patterned device using a sacrificial spacer layer. The first step in this process is to select an appropriate substrate and form a step thereon. The sacrificial layer is then applied to the substrate and a blocking layer is deposited on the sacrificial layer. The blocking layer is etched back to define the mask for the semiconductor structure and the sacrificial layer is removed. The substrate is then etched using the gap created by removal of the sacrificial layer.

Abstract: A method of processing a semiconductor device is provided. The method includes providing a semiconductor device supported by a carrier structure. The carrier structure defines a plurality of vias from a first surface of the carrier structure adjacent the semiconductor device to a second surface of the carrier structure. The method also includes extending a conductor through one of the vias such that a first end of the conductor at least partially extends below the second surface. The method also includes electrically coupling another portion of the conductor to a portion of the semiconductor device.

Abstract: A method of packaging a microchip device, an interposer for packaging, and a packaged microchip device. An interposer is placed on microchip devices. The interposer includes an aperture which extends from the interposer surface where external electrical contacts are located on the surface of the microchip devices. Electrical contacts on the microchip device surface are accessible through the aperture in order to electrically connect the electrical contacts with the external electrical contacts of the interposer. The aperture is divided into at least two openings or aperture regions, separated by a bridge. This facilitates the handling of the interposer.

Abstract: Methods of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a gate dielectric layer, and then laser annealing the substrate.

Abstract: A method for producing a semiconductor entity is described. The method includes providing a donor substrate having a zone of weakness at a predetermined depth to define a thin layer, and the donor substrate includes a bonding interface. A receiver substrate is also provided that includes at least one motif on its surface. The technique further includes bonding the donor substrate at the bonding interface to the at least one motif on the receiver substrate, and supplying sufficient energy to detach a portion of the thin layer from the donor substrate located at the at least one motif and to rupture bonds within the thin layer. The energy thus supplied is insufficient to rupture the bond at the bonding interface. Also described is fabrication of a wafer and the use of the method to produce chips suitable for use in electronics, optics, or optoelectronics applications.

Abstract: An integrated type semiconductor device that is capable of reducing cost or improving the reliability of connecting semiconductor chips together or chips to a circuit board. One embodiment of such an integrated type semiconductor device comprises a first semiconductor device (10) having a semiconductor chip (12) with electrodes (16), a stress-relieving layer (14) prepared on the semiconductor chip (12), a wire (18) formed across the electrodes (16) and the stress-relieving layer (14), and solder balls (19) formed on the wire (18) over the stress-relieving layer (14); and a bare chip (20) as a second semiconductor device to be electrically connected to the first semiconductor device (10).

Abstract: There is provided a method of forming a semiconductor device having stacked transistors. When forming a contact hole for connecting the stacked transistors to each other, ohmic layers on the bottom and the sidewall of the common contact hole are separately formed. As a result, the respective ohmic layers are optimally formed to meet requirements or conditions. Accordingly, the contact resistance of the common contact may be minimized so that it is possible to enhance the speed of the semiconductor device.

Abstract: A multi-chip memory module may be formed including two or more stacked integrated circuits mounted to a substrate or lead frame structure. The memory module may include means to couple one or more of the stacked integrated circuits to edge conductors in a memory card package configuration. Such means may include the capability to utilize bonding pads on all four sides of an integrated circuit. A lead frame structure may be divided into first and second portions. The first portion may be adapted to receive the stacked integrated circuits and the second portion may include a plurality of conductors. The first portion may also be adapted to couple at least one of the integrated circuits to power and ground conductors on the second portion. In one embodiment, the first portion may include the lead frame paddle and a conductive ring. In another embodiment, the first portion may include first and second coplanar elements.

Abstract: A dicing die-bonding film has a supporting substrate, an adhesive layer formed on the supporting substrate, and a die-bonding adhesive layer formed on the adhesive layer, and further has a mark for recognizing the position of the die-bonding adhesive layer. It is possible to provide a dicing die-bonding film in which in the case a semiconductor wafer and the dicing die-bonding film are stuck onto each other, the position of the die-bonding adhesive layer in the film can be recognized.

Abstract: An image sensor package includes a molding having a locking feature. The package further includes a snap lid having a tab, where the tab is attached to the locking feature of the molding. To form the image sensor package, a window is placed in a pocket of the molding. The snap lid is secured in place. Once secured, the snap lid presses against a peripheral region of an exterior surface of the window. The window is sandwiched between the molding and the snap lid and held in place.

Abstract: The invention relates to a method for encapsulating an electronic component, in particular a semiconductor, fixed on a carrier, comprising the processing steps of: a) placing at least one foil layer in a mould, b) placing the carrier in contact with the foil layer with the side remote from the component, and c) encapsulating the electronic component with encapsulating material, wherein the foil layer undergoes a treatment whereby the adhesion of the foil layer is increased such that it adheres to the carrier. The invention also relates to a foil material for applying during such a method.

Abstract: A method for assembling semiconductor switching elements and a heat sink in a rotary electric machine includes: a first step in which bare chips of the semiconductor switching elements are bonded to the heat sink using a good heat conductive bonding material; a second step which connects the bare chips to a wiring part by wire bonding; and a third step in which a resin which seals the bare chips and the wiring part is applied to the heat sink in a striding manner in a state that output terminal portions of the wiring part and fins of the heat sink are exposed to the outside of the resin.

Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.

Abstract: A semiconductor device comprising: a semiconductor element having a plurality of electrodes; a passivation film formed on the semiconductor element in a region avoiding at least a part of each of the electrodes; a conductive foil provided at a given spacing from the surface on which the passivation film is formed; an external electrodes formed on the conductive foil; intermediate layer formed between the passivation film and the conductive foil to support the conductive foil; and wires electrically connecting the electrodes to the conductive foil; wherein a depression tapered in a direction from the conductive foil to the passivation film if formed under a part of the conductive foil that includes the connection with the external electrodes.