Abstract: A thermally conductive protective film or layer is applied to the backside surface of a semiconductor wafer prior to a subsequent dicing operation performed on the wafer to singulate the wafer into diced semiconductor chips, during which the thin thermally conductive film minimizes and prevents chipping and cracking damage to the wafer and diced chips. During subsequent electrical operation of a diced chip, the thin thermally conductive film functions as a thermal conductor to dissipate and conduct away to a heat sink any heat generated during operation of the chip.

Abstract: Disclosed herein is a method of bonding solder pads of a flip-chip package. This invention relates to a method of bonding solder pads having different sizes to each other, when a bonding operation is executed between a chip and a PCB, between chips, or between PCBs. On a side having a larger solder pad, a general solder ball is used. Conversely, on a side having a smaller solder pad, a solder ball having a core is used. The core serves to maintain a predetermined interval between the chip and the PCB or between the chips, after the bonding operation has been completed. The solder bonded parts are aligned with each other so as to perform a final bonding operation. In a conventional flip-chip package, solder pads provided on a bonded part must have the same or similar size. According to this invention, even if the size difference between the solder pads is large, bonding is possible, thus ensuring electrical and mechanical reliability.

Abstract: At least four terminal electrodes are provided on a surface of multi-layer substrate main body. An electric functional layer is selectively provided at an internal area of said multi-layer substrate placed at a downward position of all terminal electrodes in a substrate thickness direction. A semiconductor device is flip-chip-bonded to the terminal electrodes. Thus, the semiconductor device is electrically connected to the electric functional layer at a short distance. As a result, a reduction in parasitic inductance and an improvement in high frequency characteristic can be accomplished. Generation of height variations between the terminal electrodes can be prevented, and the semiconductor device is stably flip-chip-bonded to the multi-layer substrate.

Abstract: A method for molding digital storage memory cards such as, for example, multimedia cards (MMC), secure digital cards (SD), and similar small form factor digital memory cards. A PCA subassembly including, for example, a leadframe (TSOP) package for enclosing a flash IC and a (e.g., land grad array) controller package for enclosing a controller IC are mounted on a printed wiring board within a mold cavity. A high melt flow index resin is injected into the mold cavity to form an integral, solid body within which to completely encapsulate the flash IC and controller packages and form a cover over top the flash IC package so as to maintain the required memory card height tolerance. In one embodiment, the resin material is injected downwardly into the mold cavity from locations above the respective rows of leads of the flash IC package.

Abstract: A light emitting semiconductor bonding structure includes a structure formed by bonding a substrate onto a light emitting semiconductor. The substrate is a structure containing electric circuits. The ohmic contact N electrode layer and P electrode layer are formed on the N-type contact layer and the P-type contact layer of the light emitting semiconductor respectively. A first metallic layer and a second metallic layer are formed on the surface of the substrate by means of immersion plating or deposition. The metallic layers are connected electrically to the corresponding electric signal input/output nodes of the electric circuit of the substrate. The first metallic layer and the second metallic layer are bonded onto the N electrode layer and the P electrode layer respectively through supersonic welding, and as such the light emitting semiconductor is bonded onto the substrate, and thus realizing the electric connection in-between.

Abstract: Provided are a method of manufacturing wafer-level chip-size packages and a molding apparatus suitable for practicing the method whereby a semiconductor wafer having a plurality of semiconductor chips formed thereon may be encapsulated. The semiconductor wafer, typically with a plurality of conductive bumps extending from the semiconductor chips, will be placed in a cavity formed between upper and lower molds. Injection molding of an encapsulant composition or compression molding of encapsulant sheets may then be used to apply encapsulating layers to the upper and lower surfaces of the semiconductor wafer in a substantially simultaneous manner, thereby reducing the likelihood of warping and mechanical damage to the semiconductor wafer. The wafer-level chip-size packages can then be separated from the encapsulated semiconductor wafer.

Abstract: A method of forming a leadframe package, a leadframe package formed according to the method, and a system incorporating the leadframe package. The leadframe package includes: a metallization layer comprising a paddle portion and a contact portion including contact leads; a die mounted onto the paddle portion; wirebonds connected between the die and respective ones of the contact leads; an overmold encapsulating the die, the paddle portion, the contact leads and the wirebonds; and a stiffening element encapsulated in the overmold and unconnected to electrical pathways within the leadframe package.

Abstract: A semiconductor package structure comprises a chip, a plurality of pad extension traces, a plurality of via holes, a lid and a plurality of metal traces, wherein the chip has an optical component and a plurality of pads disposed on its active surface; pad extension traces are electrically connected to the pads; the via holes penetrate the chip and are electrically connected to the pad extension traces and exposed out of side surfaces of the semiconductor package structure; the lid is adhered onto the active surface of the chip; and the plurality of metal traces is disposed on the back surface of the chip, electrically connected to the plurality of via holes, and used to define a plurality of solder pads thereon. The present invention also provides a method for manufacturing the semiconductor package structure.

Abstract: The invention relates to an LED package and proposes a method of fabricating an LED package including steps of providing a package substrate having a mounting area of an LED and a metal pattern to be connected with the LED, and plasma-treating the package substrate to reform at least a predetermined surface area of the package substrate where a resin-molded part will be formed. The method also includes mounting the LED on the mounting area on the substrate package and electrically connecting the LED with the metal pattern, and forming the resin-molded part in the mounting area of the LED to seal the LED package.

Abstract: An image sensor device and methods thereof. In an example method, a protective layer may be formed over at least one microlens. An adhesive layer may be formed over the protective layer. The adhesive layer may be removed so as to expose the protective layer. The protective layer may be removed so as to expose the at least one microlens, the exposed at least one microlens not including residue from the adhesive layer. The at least one microlens may have an improved functionality due at least in part to the lack of residue from the adhesive layer. In an example, the at least one microlens may be included in an image sensor module.

Abstract: A process includes annealing one or more plated conductive leads at a predetermined temperature. The one or more plated conductive leads are plated with one or more layers, where each layer comprises a material. The predetermined temperature is greater than or equal to approximately a melting point of one of the materials. The annealing can reduce growth formations, such as whiskers, on the one or more conductive leads. Lead frames and other devices having plated conductive leads may be subjected to the process, and the resultant plated conductive leads will have fewer growth formations than plated conductive leads not subjected to the process. The plated conductive leads may be trimmed and formed prior to or after the anneal.

Abstract: A method (300) for fabricating a lead frame (100), comprising forming a plurality of external leads (122) in a lead frame material (108), plating a metal (222) on all surfaces of the lead frame material (108), and subsequently forming a plurality of internal leads (124) in the lead frame material (108). The lead frame material (108) may comprise of a portion of a contiguous metal sheeting (204) rolled upon a first coil (202), wherein the contiguous metal sheeting (204) is fed into an external lead stamping apparatus (206), thus forming the external leads (122), and rolled onto a second coil (215). The portion is fed into a plating apparatus and plated with the metal (222), and rolled onto a third coil (218) prior to forming the plurality of internal leads (124). The third coil (218) can be unrolled into an internal lead stamping apparatus (226), thus forming the internal leads (124) of a lead frame (100).

Abstract: A process is disclosed for creating semiconductor devices such as RFID assemblies wherein an array of dies mounted to a substrate is spaced apart at a first pitch, and the substrate is removed after the positions of the dies in the array is fixed by a solidifiable substance. The solidifiable substance is then removed without changing the relative positions of the dies in the array. All or a selected portion of the array of dies is then electrically attached to a plurality of straps or interposers arranged in a corresponding array. The spacing, or pitch, between the dies in the die array may be changed before or after the substrate is removed to match the pitch of the straps or interposers in the corresponding array. An RFID device created using the process inventive is also disclosed.

Abstract: An apparatus comprises a first plurality of contacts disposed on a first side of the apparatus, adapted to engage with a first corresponding plurality of contacts on an external integrated circuit package. The apparatus further comprises a plurality of capacitive storage structures selectively coupled to the first plurality of contacts, one or more traces, and a second plurality of contacts disposed on the first side. The second plurality of contacts are adapted to engage with a second corresponding plurality of contacts on the external integrated circuit package, wherein at least two of the second plurality of contacts are adapted to be coupled to at least a first trace of the one or more traces to form a first resistive structure.

Abstract: A packaged circuit and method for packaging an integrated circuit are disclosed. The packaged circuit has a lead frame, an integrated circuit chip, and an encapsulating layer. The lead frame has first and second sections, the first section including a lateral portion, a chip mounting area and a first extension. The integrated circuit chip is mounted in the chip mounting area and is in thermal contact with the chip mounting area. The encapsulating layer has top, bottom, and first and second side surfaces. The first extension is bent to provide a first heat path from the chip mounting area to the bottom surface. The heat path connects the heat chip mounting area to the bottom surface without passing through the first and second side surfaces and provides a heat path that has less thermal resistance than the heat path through either the lateral portion or the second section.

Abstract: A method of manufacturing a semiconductor device includes providing semiconductor substrate having trenches and mesas. At least one mesa has first and second sidewalls. The method includes angularly implanting a dopant of a second conductivity into the first sidewall, and angularly implanting a dopant of a second conductivity into the second sidewall. The at least one mesa is converted to a pillar by diffusing the dopants into the at least one mesa. The pillar is then converted to a column by angularly implanting a dopant of the first conductivity into a first sidewall of the pillar, and by angularly implanting the dopant of the first conductivity type into a second sidewall of the pillar. The dopants are then diffused into the pillar to provide a P-N junction of the first and second doped regions located along the depth direction of the adjoining trench. Finally, the trenches are filled with an insulating material.

Abstract: A method and an arrangement to bond a die to a substrate of a die-substrate combination to form a microelectronic package. The method comprises: providing the die-substrate combination including a die, a substrate, pre-connection bumps and an underfill material, the pre-connection bumps and underfill material being disposed between the die and the substrate; forming joints from the pre-connection bumps at a joint formation site to obtain an intermediate package; curing the underfill material of the intermediate package at an underfill curing site to obtain the microelectronic package; using a conveying device to transfer the intermediate package from the joint formation site to the underfill curing site; and applying heat energy to the intermediate package during at least part of a transfer thereof from the joint formation site to the underfill curing site to control a temperature of the intermediate package.

Abstract: Aspects of the current invention are directed to a method of mounting a flexible printed circuit and a manufacturing method of an electric optical device. Each of the methods form semiconductor elements and first terminal portions for electrically connecting the semiconductor elements and the outside of the board. These terminal portions have are completely or partially covered with an organic film 37 and are pressed into second terminal portion on the flexible printed circuit from the direction above the organic film thereby creating an electrical connection. Optionally, an anisotropic conductive paste or anisotropic conductive film may be provided between the second terminal portion and the organic film.

Abstract: A method of producing a recording head unit including: (A) a recording head including: a plurality of recording elements; and an actuator unit including a plurality of individual electrodes which respectively correspond to the recording elements; and (B) a printed wiring board which includes conductive leads respectively having terminal portions, which is electrically connected to the individual electrodes, and through which an operating signal for operating the recording elements is supplied to the individual electrodes, the method including: forming a plurality of conductive bumps on a surface of the actuator unit such that the bumps protrude from the surface of the actuator unit, so as to be electrically connected to the individual electrodes, respectively; coating a surface of the printed wiring board with an uncured synthetic resin to form an uncured synthetic-resin layer covering the conductive leads of the printed wiring board; bringing the bumps and the terminal portions of the conductive leads into c

Abstract: A method for fabricating semiconductor packages is proposed. A plurality of substrates each having a chip thereon are prepared. Each substrate has similar length and width to the predetermined length and width of the semiconductor package. A carrier having a plurality of openings is prepared. Each opening is larger in length and width than the substrate. The substrates are positioned in the corresponding openings, and gaps between the substrates and the carrier are sealed. A molding process is performed to form an encapsulant over each opening to encapsulate the chip. An area on the carrier covered by the encapsulant is larger in length and width than the opening. After performing a mold-releasing process, a plurality of the semiconductor packages are formed by a singulation process to cut along substantially edges of each substrate according to the predetermined size of the semiconductor package. A waste of substrate material is avoided.