Abstract: A programming aid for generating interface definition files for client server programs. The system and method are responsive to an input interface definition file and one or more input source code files to extract, from one such input source code file, the semantics of procedures therein intended to be called by a remote procedure call, to detect any conflicts between the extracted semantics and the input interface definition file, to generate an output interface definition file and to report said conflicts to a user. The user can thereby develop a correct interface definition file through an iterative process by modifying the output interface definition file and using it again as the input interface definition file.

Abstract: A resource allocation manager and technique for servers within a computer system. Resources are initially allocated to servers and in order to enhance system performance, resources are reallocated based on a minimization of the maximum performance index. In one example, the server with the largest performance index is allocated additional resources and the server with the smallest performance index loses some of its resources.

Abstract: A method of scheduling successive tasks subject only to timing constraints calculates for each task upper and lower limits of the interval in which execution of that task must start. It then constructs a first series in which all the tasks are scheduled in increasing order of their lower limit and a second series in which all the asks are scheduled in increasing order of their upper limit, before constructing an initial permutation by scheduling all the tasks in the order of the first series and verifying if the initial permutation satisfies all the constraints. If not all the constraints are satisfied, the method determines in the initial permutation the first ill-placed task for which a constraint is not satisfied and a candidate task in the second series immediately preceding the ill-placed task in the second series in the current permutation.

Abstract: Systems and methods provide communication between a user-friendly terminal, such as a "home terminal" shaped to resemble a conventional telephone, and a number of service provider computers such as financial institutions. The system's application software transforms simple user commands into commands understood by the service provider computers. The network host computer supplies messages to the terminal for generating prompts needed to solicit required information from the user, and communicates with the service computers according to their respective protocols. The invention provides a packet assembler and disassembler (PAD) element within the home terminal itself, allowing fast response time for the customer at the home terminal while retaining the benefits of data error entry error correction and data transmission error correction.

Abstract: Invention maintains duplicate files in safe places. A SCAN computer program creates a TOKEN Table of an earlier file. The TOKEN Table reflects the indices of successive segments of the file and the exclusive-or (XR) and Cyclic redundancy check (CRC) products of the characters in each segment. An updated file is compared to the earlier file by comparing the XR and CRC products of segments in the updated file to the XR and CRC products in the TOKEN Table. On detecting matching products for identical segments, the next segments are compared. On mismatch, the segment (window) for the updated file is bumped one character and new XR and CRC products generated and compared. The indices of the TOKEN Table and the offsets from the start of the file of the first characters of the updated file matching segments are set forth in a Match Table.

Abstract: A cache memory having at least two modified bits for each block of data coupled to a WriteBack buffer circuit is described for transferring a fraction of the data block when a cache miss occurs. In the preferred embodiment of the present invention, the data array of the data cache is partitioned into two halves, each block of data has two modified bits. When a cache miss occurs, a replacement algorithm determines which of the lines in a given set shall be replaced. The contents of the chosen line in the data cache is written, copied to a WriteBack buffer circuit. The line of data from external memory is then written into the data cache, clearing the two modified bits in the data cache in the process. If only one modified bit is set, only half of a block of data is written back into the data cache.

Abstract: A storage management system for a memory card, which has a storage area divided into a plurality of storage units having a predetermined storage capacity. manages the storage of information in every storage unit. The storage area includes a memory allocation table (MAT) for indicating the relationship of the storage units in which a group of mutually associated information is to be stored, and a directory for indicating one of the storage units in which the beginning portion of the group of mutually associated information is to be stored. Either the MATs or the directories indicate whether or not the storage management system inhibits writing or erasing of the information in the storage units associated with the MATs or the directories. The system further includes a storage unit table which indicates whether those storage units specified by the MATs are empty or occupied.

Abstract: A quasi-synchronous information (clocking, data, control signals) transfer between a master unit A and at least one neighbor unit B offers the advantage that one transfer can occur every cycle where any interface delays are tolerated. When the master unit A sends its internal clock along with data and/or control signals to its neighbor unit B, the last named unit receives this clock and derives any and all locally required clocks from this clock. This keeps unit B exactly at the same frequency as unit A, although a phase shift occurs. Unit B also sends its internal clock along with data and/or control signals to unit A. When the clock signals arrive back at unit A, they will have exactly the same frequency as the internal clock of unit A but also an additional phase shift. Compensation of the overall phase shift will be done by a phase alignment means to which all signals are sent on their way to unit A.