Patents Examined by M. Mujtaba K Chaudry
  • Patent number: 9473273
    Abstract: According to one embodiment, a host controller includes a command generator and detector. The command generator generates a command having a retransmission flag in an argument, and transmits the generated command to a memory device. The detector detects timeout if a response from the memory device cannot be recognized within a defined time. When transmitting an initial command, the host controller clears the retransmission flag and transmits the command. If the detector detects timeout, the host controller sets the retransmission flag, and retransmits the same command as the initial command to the device. If a normal response corresponding to the initial command or retransmitted command is received, the host controller recognizes that the command is correctly executed.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: October 18, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Akihisa Fujimoto
  • Patent number: 9471429
    Abstract: A method for disk failure protection, the method may include calculating a first set of parity units by processing a first group of sets of data units that are cached in a cache memory of a storage system; calculating a second set of parity units by processing the first group of sets of data units; wherein the calculating of the second set of parity units is responsive to a first shift that was virtually introduced between each set of data units of the first group of sets of data units; and destaging the first group of sets of data units and the first and second sets of parity units to the first group of disks.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: October 18, 2016
    Assignee: INFINIDAT LTD.
    Inventor: Yechiel Yochai
  • Patent number: 9450613
    Abstract: A circuitry comprising a syndrome generator configured to generate a syndrome based on a parity check matrix and a binary word comprising a first set of bits and a second set of bits is provided. For the first set of bits an error correction of correctable bit errors within the first set is provided by the parity check matrix and for the second set of bits an error detection of a detectable bit errors within the second set is provided by the parity check matrix.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: September 20, 2016
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kern, Ulrich Backhausen, Thomas Rabenalt, Michael Goessel, Klaus Oberlaender, Christian Badack
  • Patent number: 9444497
    Abstract: A method and apparatus for adaptively tuning an integrated circuit are disclosed. For example, an integrated circuit (IC) comprises a monitored path comprising circuit elements operating on a clock signal, where a last circuit element of the circuit elements comprises a first flip flop. The IC also comprises a second flip flop operating on an early clock signal, where the early clock signal is phase shifted from the clock signal, and where the second flip flop is coupled to the monitored path prior to the last circuit element. The IC also comprises a transition detection module for detecting when an output from the first flip flop toggles, and an error prediction module to detect a potential error on the monitored path. The IC comprises a controller that is configured to scale a voltage or a frequency of the IC.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: September 13, 2016
    Assignee: XILINX, INC.
    Inventors: Sundararajarao Mohan, Tim Tuan
  • Patent number: 9430443
    Abstract: Disclosed herein is a method of generating a generator matrix for defining how to systematically code source data, the method comprising: determining source nodes for comprising a plurality of sub-stripes of source data, wherein the number of source nodes is K and the number of sub-stripes of source data comprised by each source node is S; determining redundant nodes for comprising a plurality of sub-stripes of coded data, wherein the number of redundant nodes is R and the number of sub-stripes of coded data comprised by each redundant node is S; determining values of a first generator matrix according to a systematic coding technique such that K of the rows of the generator matrix to define how to generate all of the K source nodes as comprising source data and R of the rows of the first generator matrix define how to generate all of the R redundant nodes as comprising combinations of two or more of the source nodes; generating a second generator matrix, with a first dimension (K×S) and a second dimension ((
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: August 30, 2016
    Assignee: Norwegian University of Science and Technology
    Inventors: Rune Erlend Jensen, Katina Kralevska, Danilo Gligoroski, Sindre Berg Stene
  • Patent number: 9405620
    Abstract: A data storage device including a flash memory and a controller. The controller is configured to perform a first error correction on at least one first data sector of a first page of the flash memory when a predetermined condition is satisfied, obtain a data-sector read voltage of the first data sector through the first error correction, retrieve data of a first meta-data sector of the first page by the data-sector read voltage, and perform a second error correction on the retrieved data of the first meta-data sector read by the data-sector read voltage.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: August 2, 2016
    Assignee: Silicon Motion, Inc.
    Inventor: Po-Sheng Chou
  • Patent number: 9405607
    Abstract: A memory controller comprises at least a memory control processing module and/or a distributed storage processing module. A method begins by the memory control processing module receiving a memory access request regarding a data segment. The method continues with the memory control processing module interpreting the memory access request to determine whether an error coding dispersal function of the data segment is applicable. The method continues with the memory control processing module sending the memory access request to the distributed storage processing module when the error coding dispersal function is applicable. The method continues with the distributed storage processing module performing the error coding dispersal function on the data segment to produce an error coded processed data segment. The method continues with the distributed storage processing module sending the error coded processed data segment to the memory control processing module.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: August 2, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gary W. Grube, Timothy W. Markison
  • Patent number: 9406364
    Abstract: Embodiments of an apparatus and method for encoding data are disclosed that may allow for reduced simultaneous switching output noise. The apparatus may include a row decode circuit, a column decode circuit, and a memory array. The row decode circuit and column decode circuits may be configured to decode a first portion and a second portion, respectively, of a given data word of a first plurality of data words, where each data word may include N data bits, and where N is an integer greater than one. The memory array may be configured to store a second plurality of data words where each data word may include M data bits, and where M is an integer greater than N. The memory array may be further configured to retrieve a given data word of the second plurality of data words dependent upon the decoded first and second portions.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: August 2, 2016
    Assignee: Oracle International Corporation
    Inventors: Robert P. Masleid, Don Draper, Venkat Krishnaswamy, Paul Loewenstein
  • Patent number: 9397794
    Abstract: Automatic retransmission in communications systems. An embodiment includes retransmitting data. A cyclic redundancy check (CRC) is executed on a portion of data received as part of a data stream at a receiver antenna. Feedback information of acknowledgment (ACK) or negative acknowledgement (NACK) for the portion of data is determined based on a result of the CRC. It is identified that the portion of data is to be retransmitted based on the feedback information indicating a NACK with respect to the portion of data. A retransmission mode is selected for the portion of data based on desired characteristics of the data stream, including a first mode that retransmits the portion of data on at least a first transmitter antenna while transmitting new data on at least a second transmitter antenna; and a second mode that retransmits the portion of data simultaneously on at least the first and second transmitter antennas.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: July 19, 2016
    Assignee: INVENTERGY, INC.
    Inventors: Choo Eng Yap, Lee Ying Loh
  • Patent number: 9384093
    Abstract: A data protection system having a host, a solid-state drive (“SSD”) array comprising at least three non-volatile memory express (“NVMe”) drives, each NVMe drive comprising a buffer, and a peripheral component interconnect express (“PCIe”) data bus interfacing the host and the NVMe drives. The NVMe drives are implemented with commands for implementing a RAID volume in the SSD array, wherein the commands are operable to perform RAID operations at the NVMe drives using the buffers of the NVMe drives.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: July 5, 2016
    Assignee: MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
    Inventor: Anthony Frank Aiello
  • Patent number: 9384086
    Abstract: Error checking in a computing environment at an input/output (I/O) level is facilitated by associating a cyclic redundancy check (CRC) control element (CCE) with an input/output (I/O) operation based on a command to perform the I/O operation of the computing environment. The CRC control element is used in accumulating during performance of the I/O operation an accumulated CRC value for the I/O operation to facilitate error checking of the I/O operation. By way of example, the associating and the accumulating of the accumulated CRC value may be performed within an I/O hub of the computing environment, and where data of the I/O operation is transferred in data fragments, the CRC control element is updated for each data fragment during the accumulating of the CRC context for the I/O operation.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: July 5, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Craddock, John R. Flanagan, Thomas A. Gregg
  • Patent number: 9378077
    Abstract: Errors induced by noise pulses in digital electronic circuits clocked with a clock signal are detected by providing at least one additional clock signal offset in time with respect to the clock signal by a given interval, and performing for at least one component of the circuit a comparison of correspondence between two versions of one and the same signal. The comparison is clocked by the additional clock signal and the absence of correspondence between the two versions of said signal identifies an error induced in the circuit by a noise pulse.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: June 28, 2016
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Francesco Pappalardo, Giuseppe Notarangelo, Elio Guidetti
  • Patent number: 9374199
    Abstract: A method of transmitting data in a communication network is provided, wherein the method includes receiving an error message indicating that a data packet precoded by using a first matrix and transmitted a first time by using a cooperative transmission scheme is not decoded correctly, preparing an recoded data packet by precoding the data packet using a second matrix which is different to the first matrix, and retransmitting the recoded data packet.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: June 21, 2016
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Egon Schulz, Wolfgang Zirwas
  • Patent number: 9368233
    Abstract: An amount of time and an error rate function are received, where the error rate function defines a relationship between a number of iterations associated with iterative decoding and an error rate. A testing error rate is determined based at least in part on the amount of time. The number of iterations which corresponds to the testing error rate in the error rate function is selected to be a testing number of iterations; the testing error rate and the testing number of iterations are associated with testing storage media using iterative decoding.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: June 14, 2016
    Assignee: SK Hynix Memory Solutions Inc.
    Inventors: Yu Kou, Lingqi Zeng
  • Patent number: 9361179
    Abstract: A data transmission system includes at least one transmission line. A sender is configured to send data frames to the at least one transmission line and a recipient is configured to receive the data frames from the at least one transmission line. The sender and the recipient are both configured to determine a check sum based on a plurality of corresponding data frames that are sent to and, respectively, received from the at least one transmission line. A check sum comparing unit is configured to receive and to compare the check sum determined by the sender and the corresponding check sum determined by the recipient. The check sum comparing unit is also configured to signal a transmission error or initiate a safety function when the check sums compared are not equal.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: June 7, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Dirk Hammerschmidt, Timo Dittfeld, Simon Brewerton
  • Patent number: 9356741
    Abstract: A method and system to improve the link budget of a wireless system using fast Hybrid Automatic Repeat Request (HARQ) protocol. In one embodiment of the invention, the Medium Access Control (MAC) logic in a base station determines whether the quality of the communication link with a mobile station is bad. When the MAC logic in the base station determines that the quality is bad, the base station uses a fast Hybrid Automatic Repeat Request (HARQ) protocol to indicate to the mobile station to send identical information to the base station in each of a plurality of successive or consecutive communication intervals before processing any received identical information from the mobile station. The fast HARQ protocol reduces the latency of receiving the identical information correctly, as compared with the current HARQ protocol.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: May 31, 2016
    Assignee: INTEL CORPORATION
    Inventor: Aran Bergman
  • Patent number: 9348693
    Abstract: A storage apparatus is provided. The controller of the storage apparatus includes an error correction module and a data disordering module. The error correction module is configured to perform an error correction procedure for a data packet to be written into a flash memory module of the storage apparatus for generating sequence data codes containing the data packet and corresponding error correcting codes, wherein the data packet includes a data area recording data to be written and a spare area recording data related to the data packet. The data disordering module is configured to convert the sequence data codes into non-sequence data codes, wherein the data of the data area and the spare area and error correcting codes are dispersed in the non-sequence data codes. Accordingly, it is possible to effectively increase the safety of the data packet.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: May 24, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Kuo-Yi Cheng, Chih-Kang Yeh
  • Patent number: 9344177
    Abstract: A method and apparatus is disclosed herein for performing wireless communication.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: May 17, 2016
    Assignee: NTT DOCOMO, INC.
    Inventors: Hooman Shirani-Mehr, Haralabos C. Papadopoulos, Sean A. Ramprashad, Giuseppe Caire
  • Patent number: 9344116
    Abstract: A method for determining a layer stoppage in LDPC decoding is provided. The method may include determining the occurrence of the layer stoppage to detect and record a convergence of a layer arithmetic unit after the performance of a layer decoding operation using LDPC decoding, and in a subsequent iteration operation stopping an operation of the layer arithmetic unit that has converged and repeating determining the layer stoppage for the layer arithmetic unit that has not yet converged. An output of the non-convergent layer may be diverted to the next non-convergent layer while bypassing the convergent layer without interrupting the subsequent iteration operation while maintaining the overall error correction capability.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: May 17, 2016
    Assignee: YUAN ZE UNIVERSITY
    Inventors: Cheng-Hung Lin, Tzu-Hsuan Huang, Shin-An Chou
  • Patent number: 9336820
    Abstract: A data storage device may be configured with at least one data sector sync mark. Various embodiments are generally directed to a data sector having a sync mark and stored on a data storage medium with the sync mark having either a first or second patterns and a sync circuit configured to distinguish between the two different patterns to identify a status of at least some other portion of the data sector.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: May 10, 2016
    Assignee: Seagate Technology LLC
    Inventor: Bumseok Park