Abstract: Apparatus and methods implemented therein are disclosed for relocating data stored in pages of a non-volatile memory. The number of memory chunks with invalid data in an SLC type first page is determined and if the number is above a first threshold and above a second threshold, a bit error rate (BER) for the valid data in the set of memory chunks of the first page is compared with a first BER threshold. If the BER is below the first BER threshold, an error correcting code (ECC) for valid data in a set of memory chunks of a second page is computed and the invalid data of the first page with valid data is replaced with valid data from the second page and the computed ECC. The valid data of the first and second page is relocated to a third page.

Abstract: According to one embodiment, a memory controller controlling a NAND memory having D bits/cell, includes: a code encoder which generates a code word having correction capability of t symbols; a write control unit which controls writing of the code word to the NAND memory; and a code decoder which decodes the code word read from the NAND memory, wherein the write control unit dispersedly allocates 2×D pages stored in adjacent two word lines in a block of the NAND memory to 2×D/t or more code words.

Abstract: The invention relates to a method (MET1) for transmitting data from a first network node (BS) of a radio access network of a radio communication system to a second network node (MS) of the radio access network, and wherein the method (MET1) comprises the steps of transmitting (M1/6) a first negative acknowledgement (N1) from the second network node (MS), if the second network node (MS) cannot recover error free first data (D1), the first data (D1) being data from a single data source of the radio access network or for a single data sink of the radio access network, determining (M1/11) a combination (COMB1) of the first data (D1) and of at least second data (D2) by applying a superposition of the first data (D1) and the at least second data (D2), the at least second data (D2) being further data from the single data source or for the single data sink, and transmitting (M1/18) the combination (COMB1) to the second network node (MS).

Abstract: A method begins by a dispersed storage (DS) processing module receiving a first coded matrix that includes a first plurality of pairs of coded values corresponding to first data segments of a first data stream and a second data stream. The method continues with the DS processing module receiving a second coded matrix that includes a second plurality of pairs of coded values corresponding to first data segments of a third data stream and a fourth data stream. The method continues with the DS processing module generating a new coded matrix to include a plurality of groups of selected coded values. The method continues with the DS processing module outputting the plurality of groups of selected coded values to a requesting entity in a manner to maintain time alignment of the first data segments of the first, second, third, and fourth data streams.

Abstract: A method and apparatus for transmitting enhanced uplink (EU) data is disclosed. Configuration parameters for EU operation are received, including a priority associated with each MAC-d flow and a maximum number of H-ARQ transmissions associated with each MAC-d flow. A H-ARQ process to use for transmission for a next TTI is identified. On a condition that the identified H-ARQ process is available for new data for the next TTI, data is selected for transmission over the EU channel based on MAC-d flow priority, a transmission status is set to indicate a new transmission, and the selected data is transmitted in accordance with the identified H-ARQ process. On a condition that the identified H-ARQ process is not available for new data for the next TTI, the transmission status is set to indicate a retransmission, and data associated with the identified H-ARQ process is retransmitted.

Abstract: Method and apparatus for implementing LDPC codes in an IEEE 802.11 standard system configured to operate in a Multiple-Input, Multiple-Output (MIMO) schema. A method in accordance with the present invention comprises defining a base LDPC code, having a length equal to an integer number of data carriers in an ODFM symbol, transmitting the base LDPC code over a plurality of sub-carriers, wherein the base code is transmitted at an expected phase on sub-carriers specified by the IEEE 802.11 standard system, and transmitting the base LDPC code on other sub-carriers than those specified by the IEEE 802.11 standard system, wherein the base LDPC code on the other sub-carriers is transmit offset in phase from the base LDPC code on the specified sub-carriers.

Abstract: FEC (Forward Error Correction) decoder with dynamic parameters. A novel means by which FEC parameters may be encoded into, and subsequently extracted from, a signal stream to allow for adaptive changing of any 1 or more operational parameters that govern communications across a communication channel. FEC parameters are encoded directly into a data frame such that the data frame is treated identical to all other data frames within the signal stream. When the data frame actually includes FEC parameters, it is characterized as a CP (Control Packet) type. For example, when decoding an MPEG stream, an MPEG block that includes FEC parameters, that MPEG block is characterized as a CP MPEG block. The means by which FEC parameters are encoded and extracted from the signal stream allows for much easier adaptive modification of the manner by which signal are encoded, modulated, and processed within a communication system.

Abstract: According to one embodiment, a semiconductor storage device includes a nonvolatile semiconductor memory, a temporary storage buffer that temporarily stores writing data to be written to the nonvolatile semiconductor memory, and a coding processing unit that divides coding target data of an error correction code into two or more divided data and writes an error correction code obtained by performing an error correction coding process based on the divided data stored in the temporary storage buffer to the temporary storage buffer as an intermediate code.

Abstract: Methods of operating nonvolatile memory devices may include identifying one or more multi-bit nonvolatile memory cells in a nonvolatile memory device that have undergone unintentional programming from an erased state to an at least partially programmed state. Errors generated during an operation to program a first plurality of multi-bit nonvolatile memory cells may be detected by performing a plurality of reading operations to generate error detection data and then decoding the error detection data to identify specific cells having errors. A programmed first plurality of multi-bit nonvolatile memory cells and a force-bit data vector, which was modified during the program operation, may be read to support error detection. This data, along with data read from a page buffer associated with the first plurality of multi-bit nonvolatile memory cells, may then be decoded to identify which of the first plurality of multi-bit nonvolatile memory cells are unintentionally programmed cells.

Abstract: A method of encoding user data into codevectors of an error correcting code, includes generating a first block of data symbols including user data symbols and dummy data symbols; encoding the first block using an ECC encoder to obtain a codeword comprising the first block of data symbols and a second block of parity symbols; and generating a codevector by selecting a user data portion of the user data symbols from the first block and a parity portion of the parity symbols from the second block. The sum of a number of the user data portion and a number of the parity portion is smaller than the sum of a number of the user data symbols and a number of the parity symbols of the second block.

Abstract: When an LDPC code having a code length of 16200 bits is mapped to 16 signal points, a demultiplexer performs exchanging such that when a (#i+1)-th bit from a most significant bit of code bits of 4×2 bits and a (#i+1)-th bit from a most significant bit of symbol bits of 4×2 bits of 2 consecutive symbols are represented by a bit b#i and a bit y#i, respectively, for an LDPC codes having coding rates of 7/15, b0 is allocated to y0, b1 is allocated to y2, b2 is allocated to y6, b3 is allocated to y3, b4 is allocated to y4, b5 is allocated to y1, b6 is allocated to y5, and b7 is allocated to y7.

Abstract: A system and method for improving signaling channel robustness. Additional error correction is provided for (L1) dynamic signaling that is carried in P2 symbols in such way that high time diversity can be provided. In other embodiments, transmitted services are scheduled such that services will rotate or “move” between frames, thereby ensuring that a first slot for a service is not always transmitted in the same frequency.

Abstract: The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*GT.

Abstract: A data storage device may generally be constructed and operated with at least a controller configured to identify a variance from a predetermined threshold in at least one variable resistance memory cell and upgrade a first error correction code (ECC) level to a second ECC level for the at least one variable resistance memory cell.

Abstract: Disclosed is a storage device which includes a nonvolatile memory device including a memory block a program order of which is adjusted regardless of an arrangement of memory cells, and a memory controller that performs address mapping to replace a bad page of the memory block with a normal page of the memory block.

Abstract: In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block.

Abstract: A storage module and low-complexity methods for assessing the health of a flash memory device are disclosed. In one embodiment, data is written to a subset of memory cells in a memory of a storage module. Error statistics for the subset of memory cells are determined, and cell error rate parameters for the memory are estimated by fitting the determined error statistics for the subset of memory cells with a parametric statistical model. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A semiconductor memory system may include a read data manager configured to store data read from a memory device, a likelihood value mapper configured to map likelihood values to the data output from the data manager and output mapping data, and a decoder configured to perform low density parity check decoding on the mapping data by using a parity check matrix. The parity check matrix may be a k*N×M matrix including k*N×M submatrices, where k, N and M are independently an integer equal to or greater than 2.

Abstract: Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter includes an input padding module configured to provide padded bits having padding bits added to payload bits for one or more control channels, and a scrambling module configured to apply a masking sequence to one or more of the padded bits to generate scrambled bits. Additionally, the transmitter also includes an encoding module configured to perform forward error correction encoding and rate matching on the scrambled bits to obtain a required number of control channel output bits, and a transmit module configured to transmit the control channel output bits for one or more control channels.

Abstract: A method for data storage includes encoding each of multiple data items individually using a first Error Correction Code (ECC) to produce respective encoded data items. The encoded data items are stored in a memory. The multiple data items are encoded jointly using a second ECC, so as to produce a code word of the second ECC, and only a part of the code word is stored in the memory. The stored encoded data items are recalled from the memory and the first ECC is decoded in order to reconstruct the data items. Upon a failure to reconstruct a given data item from a respective given encoded data item by decoding the first ECC, the given data item is reconstructed based on the part of the code word of the second ECC and on the encoded data items other than the given encoded data item.