Abstract: One embodiment of the invention is a recursive partitioning method that place circuit elements in an IC layout. This method initially defines a number of partitioning lines that divide an IC region into several sub-regions (also called slots) for a net in the region, the method then identifies the set of sub-regions (i.e., the set slots) that contain the circuit elements (e.g., the pins or circuit modules) of that net. The set of sub-regions for the net represents the net's configuration with respect to the defined partitioning lines. Next, the placement method identifies attribute or attributes of a connection graph that models the net's configuration with respect to the partitioning lines. The connection graph for each net provides a topology of interconnect lines that connect the slots that contain the net's circuit elements. According to some embodiments of the invention, the connection graph for each net can have edges that are completely or partially diagonal.

Abstract: A system and method for graphically displaying modules and resources within a chip design software application. The system and method provide a graphical interface which relate both a module and the associated resource. This graphical interface utilizes highlights of both the module and the associated resource in patterns, grayscales, or colors to graphically illustrate the relationship between the module and the associated resource. The system and method also provide a graphical interface which illustrates a fixed group and unfixed group of resources associated with a particular module. The unfixed group of resources can be iterated to a next possible location on the chip that would satisfy the requirements of the associated module. Any fixed group of resources can be selected as the unfixed group by selecting that group of resources.

Abstract: Method and circuits to create reduced field programmable gate arrays (RFPGA) from the configuration data of field programmable gate arrays (FPGA) are disclosed. The configurable elements of the FPGA are replaced with standard cell circuits that reproduce the functionality of the configured FPGA. Specifically, reduced logic blocks are derived from the configuration data of configurable logic blocks. Similarly, reduced input/output blocks and reduced matrices are derived from the configuration data for input/output blocks and programmable switch matrices of the FPGA, respectively. The reduced logic.blocks are arranged in a similar layout to the original CLBs so that timing relationships remain similar in the RFPGA and FPGA. The actual timing of the RFPGA can be modified by increasing or decreasing the timing delay on various signal paths based on the FPGA design or additional timing constraints.

Abstract: A method for preferentially shielding a signal to increase implicit decoupling capacitance is provided. The signal is preferentially shielded by using a probability of the signal being at a specific value to determine where to route the signal. Further, an integrated circuit that preferentially shields a signal to increase decoupling capacitance by 2using a probability of the signal being at a specific value to determine where to route the signal. Further, a computer system for preferentially shielding a signal to increase decoupling capacitance by using a probability of the signal being at a specific value to determine where to route the signal. Further, a computer readable medium having executable instructions for preferentially shielding a signal to increase implicit decoupling capacitance by using a probability of the signal being at a specific value to determine where to route the signal.

Abstract: A methodology for translating multiple bit conditional expressions of a non-Verilog hardware description language (HDL) program, not readily recognized by Verilog HDL, which can then be used to realize a logic circuit design embodied by the non-Verilog HDL program. Conditional IF expressions occurring within the HDL program that are not recognized by Verilog HDL are processed so that they can be accordingly translated to Verilog HDL syntax. If the conditional IF expression is a multiple-bit expression, a binary operator statement having bit-wise binary operators, including two AND operators, one OR operator, and one NOT operator, that is equivalent to the conditional IF expression is created.

Abstract: A method estimates the capacitance effects of an interconnect prior to routing of an integrated circuit (IC) design, as follows. The design is divided into areas. Capacitance effects for each area are estimated based on the congestion ratios within the area. The congestion ratios for each area are derived from estimations of the demand for routing resources in each area for each net in the net-list included in the IC design. Coupling vectors are derived for each area from the congestion ratios. Capacitance effects for each area are then estimated by looking up a database using the coupling vectors. The resulting per-area capacitance effects are then used to estimate capacitance in an interconnect traversing the area. The total capacitance effects due to an interconnect traversing multiple areas is determined by applying the per-area capacitance effects for the areas to the dimensions of portions of the interconnect traversing each of the areas.

Abstract: A high-level synthesis method comprising the steps of converting an operating description describing one or more operations to a control data flow graph (CDFG) including one or more nodes representing the one or more operations and one or more I/O branches representing a flow of data, scheduling the CDFG obtained by the converting step, and allocating one or more logic circuits required for executing the CDFG obtained by the scheduling step. A portion of the CDFG in the converting step is subjected to logical synthesis in advance to generate a node, and the portion of the CDFG is replaced with that node.

Abstract: A method for generating an asynchronous controller includes a process controller formation step S100 of forming a signal transition graph representing a state of change in input/output signals of a plurality of process controllers PC1˜PC4 for outputting control signals necessary for executing a process corresponding to a node in a data flow graph showing a performance sequence between a plurality of nodes each representing a process and a plurality of processes, a process sequencing controller formation step S400 of forming a signal transition graph of a process sequencing controller PSC according to a performance sequence of the process controllers PC1˜PC4 from the data flow graph, and a logic synthesis step S500 of generating an asynchronous controller in a logic synthesis program, by using the state of change in the input/output signals on the signal transition graph of the process controllers PC1˜PC4 formed in the process controller formation step S100 and the state of change in the inpu

Abstract: An integrated circuit (IC) includes a number of function blocks (FB), of which at least one is re-configurable. Each of the FBs may be a reconfigurable function or a non-reconfigurable function or recursively expanded with additional “nested” function blocks. The IC further includes a number of input pins, a number of output pins, and a number of crossbar devices. The elements, at least at the IC level, are coupled in a manner such that all input signals are provided to the FBs through a first subset of the crossbar devices, all internal signals are routed from one FB to another FB through a second subset of crossbar devices, and all output signals are routed from the FBs to the output pins through a third subset of crossbar devices. To increase routability and speed each of the crossbar device output has a single fanout. Additionally, each of the crossbar devices may provide only one input to each other crossbar device.

Abstract: A semiconductor apparatus, includes a semiconductor substrate, a first wiring, a second wiring and a capacitance cell. The first wiring is provided in the semiconductor substrate. The second wiring is provided in the semiconductor substrate. The capacitance cell includes a bypass capacitor connecting the first wiring to the second wiring.

Abstract: Embodiments of the present invention generate equations that model a synchronous circuit that contains sequential elements, which may include transparent elements, and a plurality of multiple-phase clocks. Phase-related information is assigned to nodes of the circuit. The phase-related information describes input and output characteristics at nodes of the circuit as the characteristics relate to clock phases. Equations are formed that model signals at the circuit nodes based on the phase-related information.

Abstract: Clock delays are changed in a clock network of an ASIC. Global skew optimization is achieved by restructuring a clock domain to balance clock delays in the domain, and by equalizing clock delays of several domains of a group that have timing paths between them. Clock delays are equalized using buffer chains affecting all leaves of the respective domain, and an additional delay coefficient that equalizes clock delay. The clock insertion delays are changed for each group by restructuring the buffers in the group, based on both the data and clock logics to optimize the paths. Local skew optimization is achieved by restructuring the clock domain using a heuristic algorithm and re-ordering the buffers of the domain. A computer program enables a processor to carry out the processes.

Abstract: A method, system and apparatus is provided to perform noise analysis of electrical circuits. The method and system partitions an original multi-port circuit to a reduced circuit model having a specific layout configuration. The reduced circuit model may have a variety of configurations. Then an input signal is applied to a first port of the reduced circuit model using the specific layout configuration and an output signal is measured from a second port of the reduced circuit model. The process continues until all input ports which may contribute noise to the circuit are measured and then the results are calculated to determine the total output of simulated noise experienced by the circuit. The calculated output results of the reduced circuit model are then used to determine whether the original circuit is designed to withstand the quantity of noise experienced by the reduced circuit model.