Abstract: This invention discloses a photomask manufacturing method. A pattern dimensional map is generated by preparing a photomask in which a mask pattern is formed on a transparent substrate, and measuring a mask in-plane distribution of the pattern dimensions. A transmittance correction coefficient map is generated by dividing a pattern formation region into a plurality of subregions, and determining a transmittance correction coefficient for each of the plurality of subregions. The transmittance correction value of each subregion is calculated on the basis of the pattern dimensional map and the transmittance correction coefficient map. The transmittance of the transparent substrate corresponding to each subregion is changed on the basis of the transmittance correction value.

Abstract: A method and system for computing Fourier coefficients for a Fourier representation of a mask transmission function for a lithography mask. The method includes: sampling a polygon of a mask pattern of the lithography mask to obtain an indicator function which defines the polygon, performing a Fourier Transform on the indicator function to obtain preliminary Fourier coefficients, and scaling the Fourier coefficients for the Fourier representation of the mask transmission function, where at least one of the steps is carried out using a computer device.

Abstract: A library cell is designed, and then the width of the polys is increased, and the polys and contacts are shifted in order to maintain poly-to-poly and contact-to-poly spacing. The method can be used in association with a 45 nm digital library cell. Specifically, a library cell having 40 nm polys is designed, and then the width of each of the polys is increased by 5 nm to 45 nm, and the polys and contacts are shifted in order to maintain poly-to-poly and contact-to-poly spacing. The poly lines and contacts can be shifted by starting at the center and going out radially, or by beginning at the perimeter and moving radially inward. The method can be used with any library cell design which is entirely GDS based, including, for example, 32 nm library cell design.

Abstract: The present invention aims to improve accuracy of a planar manufacturing drawing used to instruct manufacture of a three-dimensional structure in a planar form. According to path plan information is acquired by a path plan information acquisition unit 11a and manufacturing requirement information is acquired by a manufacturing requirement information acquisition unit, a layout configuration production unit 11c produces a layout configuration model in which the three-dimensional structure is laid out in a planar manner based on a manufacture layout and distortion of the wire harness. Then, a simulation unit 11d simulates a transformation from the layout configuration model to the mounting configuration model with which the three-dimensional structure is mounted to a mount object. Then, an evaluation item evaluating unit 11e evaluates a predetermined evaluation item by comparing the simulation result and the three-dimensional structure indicated by the path plan information.

Abstract: A technique for reconstructing a mask pattern corresponding to a photo-mask using a target mask pattern (which excludes defects) and an image of at least a portion of the photo-mask is described. This image may be an optical inspection image of the photo-mask that is determined using inspection optics which includes an optical path, and the reconstructed mask pattern may include additional spatial frequencies than the image. Furthermore, the reconstructed mask pattern may be reconstructed based on a characteristic of the optical path (such as an optical bandwidth of the optical path) using a constrained inverse optical calculation in which there are a finite number of discrete feature widths allowed in the reconstructed mask pattern, and where a given feature has a constant feature width. Consequently, the features in the reconstructed mask pattern may each have the constant feature width, such as an average critical dimension of the reconstructed mask pattern.

Abstract: A design method of a semiconductor integrated circuit sets an area having apices of opposing corners of a position of a start point logic cell and a position of an end point logic cell to a repeater search area, adds free area information to the repeater search area, sets a drive boundary in the repeater search area based on a drive ability of the start point logic cell, searches a repeater candidate that can be arranged in an area of the drive boundary based on the free area information, calculates a delay time from the start point logic cell to the end point logic cell based on delay time information and a coordinate of the repeater candidate that is searched, and determines a repeater arranged between the start point logic cell and the end point logic cell from the repeater candidate based on the delay time that is calculated.

Abstract: An aspect of the present invention is a method for laying out a power wiring of a semiconductor device. The method includes: modeling the power wiring as an analysis model including a plurality of nodes and a plurality of element resistors provided between the plurality of nodes neighboring each other; obtaining voltage values of the plurality of nodes by a circuit simulation; searching a path of a current flowing into a node of the plurality of nodes when an IR drop violation exists in the voltage values, the node having a maximum value of the IR drop violation; selecting a bottleneck element resistor from among the plurality of element resistors included in the path; and changing a resistance value of the bottleneck element resistor.

Abstract: A large block synthesis (LBS) process pre-optimizes selected submacros by synthesizing the submacros using timing assertions and placement abstracts, removing placement information, and assigning weights to the internal nets of the submacros that are much higher than weights used for external (e.g., top-level) nets. The timing assertions include an input arrival time, a required output arrival time, and an output pin capacitance loading for the logic block, and the placement abstract is generated by condensing input and output pins of the logic block at a center of gravity of the logic block. The submacros to be pre-optimized can automatically be identified using an attribute to indicate pre-optimization, or by determining that the submacro is one of many instances in the design. The higher weights for the submacro nets define soft-bounds for the logic which still allow relocation of submacro components. The pre-optimization results in significantly reduced synthesis runtime.

Abstract: A two-dimensional transmission cross coefficient is obtained based on a function representing a light intensity distribution formed by an illumination apparatus on a pupil plane of the projection optical system and a pupil function of the projection optical system. Based on the two-dimensional transmission cross coefficient and data of a pattern on an object plane of the projection optical system, an approximate aerial image is calculated by using at least one of plural components of an aerial image on an image plane of the projection optical system. Data of a pattern of an original is produced based on the approximate aerial image.

Abstract: Systems and methods for creating and implementing two-dimensional (2D), image-based design rules (IBDRs) are disclosed. Techniques for creating 2D IBDR can include identifying a search pattern that is representative of a 2D pattern of interest of a design, creating a pattern representation based on the search pattern, defining an anchor point for the pattern representation, and assigning weights to elements of the pattern representation. The 2D MDR can be used in systems and method for searching a design by comparing the 2D IBDR to the design. A number of 2D IBDRs can be merged into a subset of similar 2D IBDRs by characterizing desired rule geometries, sorting the 2D IBDRs into groups according to the desired rule geometries, merging the groups of 2D IBDRs into a single representative search pattern. Additionally, standard design rules can be created from the disclosed 2D IBDRs.

Abstract: A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.

Abstract: A method, system, and computer usable program product for equation based retargeting of design layouts are provided in the illustrative embodiments. A set of desirable combination of values of a set of layout parameters of the design layout is determined. A desirable region that includes the set of the desirable combination of values is determined. An equation is computed to determine a retargeting value for a first combination of values of the set of layout parameters with respect to the desirable region. Instructions are generated to adjust a value in the first combination to generate a second combination of values of the set of layout parameters such that the second combination falls in the desirable region. A shape in the design layout is retargeted such that the retargeted shape uses the second combination of values of the set of layout parameters. The IC is manufactured using the retargeted shape.

Abstract: Methods and systems for simulating logic may translate logic design into executable code for a multi-processor based parallel logic simulation device. A system may implement one or more parallel execution methods, which may include IPMD, MPMD, and/or DDMT.

Abstract: A method and a computer system for designing an optical photomask for forming a prepattern opening in a photoresist layer on a substrate wherein the photoresist layer and the prepattern opening are coated with a self-assembly material that undergoes directed self-assembly to form a directed self-assembly pattern. The methods includes: generating a mask design shape from a target design shape; generating a sub-resolution assist feature design shape based on the mask design shape; using a computer to generate a prepattern shape based on the sub-resolution assist feature design shape; and using a computer to evaluate if a directed self-assembly pattern of the self-assembly material based on the prepattern shape is within specified ranges of dimensional and positional targets of the target design shape on the substrate.

Abstract: Approaches for generating functions for activating processes in a simulation model. At least two mutually exclusive sub-ranges of a plurality of bits of a net of the circuit design are determined. A respective process set associated with each sub-range of the plurality of bits is determined. The specification of a wakeup function includes for each sub-range of the plurality of bits, a test for a change in value of at least one bit in the sub-range of the plurality of bits, and an initiation of each process in the associated process set in response to a detected change in value of the at least one bit. The specification also includes control, responsive to a detected change in value of at least one bit in one of the sub-ranges, that bypasses a test for a change in value of at least one bit in at least one other of the sub-ranges.

Abstract: Systems and methods for creating and implementing two-dimensional (2D), image-based design rules (IBDRs) are disclosed. Techniques for creating 2D IBDR can include identifying a search pattern that is representative of a 2D pattern of interest of a design, creating a pattern representation based on the search pattern, defining an anchor point for the pattern representation, and assigning weights to elements of the pattern representation. The 2D MDR can be used in systems and method for searching a design by comparing the 2D IBDR to the design. A number of 2D IBDRs can be merged into a subset of similar 2D IBDRs by characterizing desired rule geometries, sorting the 2D IBDRs into groups according to the desired rule geometries, merging the groups of 2D IBDRs into a single representative search pattern. Additionally, standard design rules can be created from the disclosed 2D IBDRs.

Abstract: Multistage synthesis of hardware function operation descriptions is provided, which facilitates placement of logic cells in an integrated circuit design layout, and includes: parsing hardware function operation descriptions of a circuit to identify multiple instantiations of a type of logic function; performing, without shape restriction, a first synthesis on each logic function type identified as having multiple instantiations and producing an irregular-shaped logic unit layout for that logic function type; establishing an irregular-shaped blocking mask corresponding to a respective irregular-shaped logic unit layout produced by the first synthesis; creating a partial circuit layout by placing each irregular-shaped blocking mask multiple times corresponding to the multiple instantiations of the respective logic function type; and performing, employing the partial circuit layout, a second synthesis on the balance of the hardware function operation descriptions of the circuit outside the multiple instantiation

Abstract: The technology disclosed relates to variable tapers to resolve varying overlaps between adjacent strips that are lithographically printed. Technology disclosed combines an aperture taper function with the variable overlap taper function to transform data and compensate for varying overlaps. The variable taper function varies according to overlap variation, including variation resulting from workpiece distortions, rotor arm position, or which rotor arm printed the last stripe. Particular aspects of the present invention are described in the claims, specification and drawings.

Abstract: Some embodiments provide a system that improves performance during parameterized cell instantiation in an electronic design automation (EDA) application. During operation, the system persists evaluation results associated with a parameterized cell in the design within a session of the EDA application so that the evaluation results are available even after they have been flushed from memory. Further, the system can persist the evaluation results across sessions of the EDA application. Next, the system uses the persisted evaluation results to instantiate the parameterized cell without re-evaluating the parameterized cell. Finally, the system discards the persisted evaluation results based at least on a dependency associated with the parameterized cell.

Abstract: Mechanisms are provided in a design environment for minimizing memory array representations for enhanced synthesis and verification. The design environment comprises one mechanism to compress the width of arrays using disconnected pin information. The design environment comprises another mechanism to simplify the enable conditions of array ports using “don't care” computations. The design environment comprises yet another mechanism to reduce address pins from an array through analysis of limitations of readable addresses.