Abstract: A semiconductor device includes: a gate electrode groove formed in contact with a drift region, a well region, and a source region; a gate electrode formed on a surface of the gate electrode groove via an insulating film; a source electrode groove in contact with the gate electrode groove; a source electrode electrically connected to a source region; and a gate wiring electrically insulated from the source electrode and formed inside the source electrode groove in contact with the gate electrode.

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer, a carrier transit layer, a carrier supply layer, a gate, a source electrode and a drain electrode. The buffer layer is on a substrate. The carrier transit layer is on the buffer layer. The carrier supply layer is on the carrier transit layer. The gate is on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the gate, wherein each of the source electrode and the drain electrode includes a conductive layer and a conductive oxide layer stacked from bottom to top.

Abstract: A display apparatus includes a display region and a peripheral region adjacent to the display region. The display apparatus further includes a first flexible substrate (FFS), a driving circuit (DC), a conductive pattern (CP), a conductive line, a light-emitting device, and a support substrate. The FFS includes a first surface and a second surface opposite the first surface. The second surface includes, in the peripheral region, a cavity extending into the FFS. The DC is on the first surface and includes at least one transistor. The CP is in the cavity and is partially exposed by the cavity. The conductive line electrically connects the CP to the DC. The light-emitting device is in the display region and is electrically connected to the DC. The support substrate is on the second surface. In a view normal to the second surface, the support substrate is spaced apart from the CP.

Abstract: A method of forming a fin field effect device is provided. The method includes forming one or more vertical fins on a substrate and a fin template on each of the vertical fins. The method further includes forming a gate structure on at least one of the vertical fins, and a top spacer layer on the at least one gate structure, wherein at least an upper portion of the at least one of the one or more vertical fins is exposed above the top spacer layer. The method further includes forming a top source/drain layer on the top spacer layer and the exposed upper portion of the at least one vertical fin. The method further includes forming a sacrificial spacer on opposite sides of the fin templates and the top spacer layer, and removing a portion of the top source/drain layer not covered by the sacrificial spacer to form a top source/drain electrically connected to the vertical fins.

Abstract: Provided is a semiconductor manufacturing apparatus including: a container in which a processing chamber is installed; a stage installed in the processing chamber and configured to hold a semiconductor substrate; a gas supply line configured to supply reactive gas to the processing chamber; and a vacuum line configured to exhaust the processing chamber, wherein the semiconductor substrate includes a high-k insulating film, and as the reactive gas, mixed gas including complex-forming gas forming a volatile organometallic complex by reacting with a metal element included in the high-k insulating film and complex stabilizing material gas that increases stability of the organometallic complex is supplied.

Abstract: A light emitting device includes a first light emitting element and a first covering member. The first light emitting element has a peak emission wavelength in a range of 430 nm or greater and less than 490 nm. The first covering member covers the first light emitting element, and contains a first phosphor having a peak emission wavelength in a range of 490 nm and 570 nm or less. A content of the first phosphor is 50 weight % or greater with respect to a total weight of the first covering member. A mixed color light in which light emitted from the first light emitting element and light emitted from the first phosphor are mixed has an excitation purity of 60% or greater on a 1931CIE chromaticity diagram. The first phosphor contains secondary particles.

Abstract: A die seal ring and a manufacturing method thereof are provided. The die seal ring includes a substrate, a dielectric layer, and conductive layers. The dielectric layer is disposed on the substrate. The conductive layers are stacked on the substrate and located in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is disposed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is disposed between a sidewall of the second conductive portion and the dielectric layer. The die seal ring and the manufacturing method thereof can effectively prevent cracks generated during the die sawing process from damaging the circuit structure.

Abstract: The present disclosure describes an exemplary fabrication method of a p-type fully strained channel that can suppress the formation of {111} facets during a silicon germanium epitaxial growth. The exemplary method includes the formation of silicon epitaxial layer on a top, carbon-doped region of an n-type region. A recess is formed in the silicon epitaxial layer via etching, where the recess exposes the top, carbon-doped region of the n-type region. A silicon seed layer is grown in the recess, and a silicon germanium layer is subsequently epitaxially grown on the silicon seed layer to fill the recess. The silicon seed layer can suppress the formation of growth defects such as, for example, {111} facets, during the silicon germanium epitaxial layer growth.

Abstract: Methods of forming a silicon oxide layer and a semiconductor structure are disclosed. The method of forming the silicon oxide layer includes the following steps. A silicon-containing precursor, an oxygen-containing precursor and an oxygen radical are provided to form a silicon oxide layer containing water. A thermal process is performed on the silicon oxide layer to diffuse the water into the silicon oxide layer and oxidize the silicon oxide layer by using the water as oxidizer.

Abstract: A pixel arrangement structure includes a plurality of pixel rows. Two adjacent ones of the pixel rows are disposed to be misaligned with each other. Each of the pixel rows includes a plurality of pixels. Each of the pixels includes a first sub pixel; a second sub pixel; and a third sub pixel. The first sub pixel in an N+1-th pixel row is disposed adjacent to the first sub pixel of one of the pixels in an N+2-th pixel row, the second sub pixel in an N-th pixel row is disposed adjacent to the second sub pixel of one of the pixels in the N+1-th pixel row, and N is a positive odd number greater than or equal to 1. An organic light-emitting diode display device is further provided.

Abstract: Solid state transducer devices with independently controlled regions, and associated systems and methods are disclosed. A solid state transducer device in accordance with a particular embodiment includes a transducer structure having a first semiconductor material, a second semiconductor material and an active region between the first and second semiconductor materials, the active region including a continuous portion having a first region and a second region. A first contact is electrically connected to the first semiconductor material to direct a first electrical input to the first region along a first path, and a second contact electrically spaced apart from the first contact and connected to the first semiconductor material to direct a second electrical input to the second region along a second path different than the first path. A third electrical contact is electrically connected to the second semiconductor material.

Abstract: An electronic component includes a die, a first protective layer, a second protective layer, a first conductive pillar and a second conductive pillar. The die includes a conductive pad. The first protective layer is disposed on the die. The first protective layer defines a first opening to expose the conductive pad of the die. The second protective layer is disposed on the first protective layer. The second protective layer defines a second opening and a first recess. The second opening exposes the conductive pad of the die. The first conductive pillar is disposed within the second opening and electrically connected to the conductive pad. The second conductive pillar is disposed within the first recess. A height of the first conductive pillar is substantially equal to a height of the second conductive pillar. A bottom surface of the first recess is disposed between a top surface of the first protective layer and a top surface of the second protective layer.

Abstract: A semiconductor device includes a semiconductor layer, a metal layer electrically contacting the semiconductor layer, and a two-dimensional material layer between the semiconductor layer and the metal layer and having a two-dimensional crystal structure.

Abstract: Described is a semiconductor device including a first N-type well region disposed in a substrate and a second N-type well region in contact with the first N-type well region, a source region disposed in the first N-type well region, a drain region disposed in the second N-type well region, and a first gate electrode and a second gate electrode disposed spaced apart from the drain region. A maximum vertical length of the source region in a direction vertical to the first or second gate electrode is greater than a maximum vertical length of the drain region in the direction in a plan view.

Abstract: A film having filling capability is deposited by forming a viscous polymer in a gas phase by striking an Ar, He, or N2 plasma in a chamber filled with a volatile hydrocarbon precursor that can be polymerized within certain parameter ranges which define mainly partial pressure of precursor during a plasma strike, and wafer temperature.

Abstract: Disclosed herein are a light-emitting diode (LED) package structure and a method producing the same. The LED package structure includes a substrate; and a light-emitting unit disposed on the substrate. The light-emitting unit comprises a gallium nitride-based semiconductor, and a polymeric layer encapsulating the gallium nitride-based semiconductor. Also disclosed herein is a method of producing the LED package structure. The method comprises: providing a substrate; electrically connecting a gallium nitride-based semiconductor onto the substrate; overlaying the gallium nitride-based semiconductor with a slurry comprising a resin and a plurality of composite fluorescent gold nanocluster; and curing the slurry overlaid on the gallium nitride-based semiconductor to form a solidified polymeric layer.

Abstract: A Si-free C-containing film having filling capability is deposited by forming a viscous polymer in a gas phase by striking an Ar, He, or N2 plasma in a chamber filled with a volatile hydrocarbon precursor that can be polymerized within certain parameter ranges which define mainly partial pressure of precursor during a plasma strike, and wafer temperature.

Abstract: Disclosed herein are composite fluorescent gold nanoclusters with high quantum yield, as well as methods for manufacturing the same. According to some embodiments, the composite fluorescent gold nanocluster includes a gold nanocluster and a capping layer that encapsulates at least a portion of the outer surface of the gold nanocluster. The capping layer includes a matrix made of a benzene-based compound, and multiple phosphine-based compounds distributed across the matrix.

Abstract: A transistor having high field-effect mobility is provided. In order that an oxide semiconductor layer through which carriers flow is not in contact with a gate insulating film, a buried channel structure in which the oxide semiconductor layer through which carriers flow is separated from the gate insulating film is employed. Specifically, an oxide semiconductor layer having high conductivity is provided between two oxide semiconductor layers. Further, an impurity element is added to the oxide semiconductor layer in a self-aligned manner so that the resistance of a region in contact with an electrode layer is reduced. Further, the oxide semiconductor layer in contact with the gate insulating layer has a larger thickness than the oxide semiconductor layer having high conductivity.

Abstract: A method of manufacturing a semiconductor device having a metal oxide film with workpiece accommodated in a chamber, includes: supplying a precursor gas containing a metal complex into the chamber to form a precursor layer on the workpiece from the precursor gas; supplying an oxidizing gas into the chamber to oxidize the precursor layer so that a metal oxide layer is formed, the oxidizing gas being a gas containing H2O or a gas having a functional group containing hydrogen atoms in the metal complex and containing an oxidant to generate H2O by reaction with the functional group; supplying an H2O removal gas containing alcohols or amines into the chamber to remove H2O adsorbed onto the metal oxide layer; and executing a plurality of cycles each including the supplying a precursor gas and the supplying an oxidizing gas. At least some of the cycles includes the supplying an H2O removal gas.