Abstract: A method of manufacturing a semiconductor package includes: coupling a semiconductor die to a protection layer; forming a first redistribution layer over the semiconductor die, wherein the first redistribution layer includes a first conductive plate and a first dielectric material laterally surrounding the first conductive plate; forming a recess in the first redistribution layer, wherein the recess is over the first conductive plate and defined by the first dielectric material; depositing an insulating film in the recess with a second dielectric material of a dielectric constant greater than a dielectric constant of the first dielectric material; and forming a second redistribution layer including a second conductive plate over the insulating film. The insulating film electrically isolates the first conductive plate from the second conductive plate, and one of the first conductive plate and the second conductive plate is configured to radiate or receive electromagnetic wave.

Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming an oxide film on a target layer, forming a first mask film on the oxide film, wherein the first mask film contains a semiconductor material and has a first thickness and a first etch selectivity with respect to the oxide film, forming a second mask film on the first mask film, wherein the second mask film contains a metal and has a second thickness smaller than the first thickness and a second etch selectivity larger than the first etch selectivity with respect to the oxide film, forming a second mask film pattern by patterning the second mask film, forming a first mask film pattern by patterning the first mask film, etching some portions of the oxide film by using the second mask film pattern as an etch mask film, and etching the rest of the oxide film by using the first mask film pattern as an etch mask film to form a hole, wherein the target layer is exposed via the hole.

Abstract: Provided is a technique which includes forming on a substrate an oxide film containing silicon or a metal element and doped with a dopant by performing a cycle a predetermined number of times, wherein the cycle includes sequentially and non-simultaneously performing: (a) supplying a first gas to the substrate wherein the first gas is free of chlorine and contains boron or phosphorus as the dopant; (b) supplying a second gas to the substrate wherein the second gas contains silicon or the metal element; and (c) supplying a third gas to the substrate wherein the third gas contains oxygen.

Abstract: Conductive structure technology is disclosed. In one example, a conductive structure can include an interconnect and a plurality of conductive layers overlying the interconnect. Each conductive layer can be separated from an adjacent conductive layer by an insulative layer. In addition, the conductive structure can include a contact extending through the plurality of conductive layers to the interconnect. The contact can be electrically coupled to the interconnect and insulated from the plurality of conductive layers. Associated systems and methods are also disclosed.

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over a target layer, forming a second mask layer over the first mask layer, patterning the second mask layer, forming a third mask layer over the patterned second mask layer, patterning the third mask layer, etching the first mask layer using both the patterned second mask layer and the patterned third mask layer as a combined etch mask, removing the patterned third mask layer to expose a portion of the first mask layer, performing a trim process on the exposed portion of the first mask layer, and etching the target layer using the first mask layer to form openings in the target layer.

Abstract: An example device includes a doped absorption region to receive optical energy and generate free electrons from the received optical energy. The example device also includes a doped charge region to increase an electric field. The example device also includes an intrinsic multiplication region to generate additional free electrons from impact ionization of the generated free electrons. The example device includes a doped contact region to conduct the free electrons and the additional free electrons.

Abstract: To allow a metal oxide film composed mainly of O and at least one of Hf and Zr to exhibit ferroelectric properties. After deposition of a hafnium oxide film on a semiconductor substrate via an insulating film, the semiconductor substrate is exposed to microwaves to selectively heat the hafnium oxide film. This makes it possible to form a larger number of orthorhombic crystals in the crystals of the hafnium oxide film. The hafnium oxide film thus obtained can therefore exhibit ferroelectric properties without adding, thereto, an impurity such as Si. This means that the hafnium oxide film having a reverse size effect can be used as a ferroelectric film of a ferroelectric memory cell and contributes to the manufacture of a miniaturized ferroelectric memory cell.

Abstract: A method for depositing an oxide film on a substrate by thermal ALD and PEALD, includes: providing a substrate in a reaction chamber; depositing a first oxide film on the substrate by thermal ALD in the reaction chamber; and without breaking a vacuum, continuously depositing a second oxide film on the first oxide film by PEALD in the reaction chamber.

Abstract: A transistor includes a semiconductor layer comprising a channel portion, a first contact portion and a second contact portion, a gate electrode facing the floating gate, and a floating gate disposed between the semiconductor layer and the gate electrode, the floating gate being insulated from the semiconductor layer and the gate electrode. The floating gate comprises an oxide semiconductor.

Abstract: A method for producing a via in a wafer includes providing a wafer, comprising silicon. The method includes producing a conductive region, in the form of a conductor track, preferably composed of polycrystalline silicon, in the wafer. The method includes producing a hole in the wafer such that the hole is fluidically connected to the conductive region and the sidewalls of the hole comprise silicon. The method includes applying a tungsten hexafluoride-resistant protective layer, produced from silicon oxide, in the region of the surface of the hole that is to be produced or has been produced, such that an opening of the hole is free of a protective layer. The method includes applying tungsten hexafluoride to the hole and the region of the opening of the hole by a reducing-agent-free vapor phase deposition process, preferably in the form of a CVD process, for producing the via.

Abstract: An embodiment of the invention comprises a method of forming a transistor comprising forming a gate construction having an elevationally-outermost surface of conductive gate material that is lower than an elevationally-outer surface of semiconductor material that is aside and above both sides of the gate construction. Tops of the semiconductor material and the conductive gate material are covered with masking material, two pairs of two opposing sidewall surfaces of the semiconductor material are laterally exposed above both of the sides of the gate construction. After the covering, the semiconductor material that is above both of the sides of the gate construction is subjected to monolayer doping through each of the laterally-exposed two opposing sidewall surfaces of each of the two pairs and forming there-from doped source/drain regions above both of the sides of the gate construction.

Abstract: An integrated circuit package includes a die, a plurality of conductive vias, an alignment mark and an insulating encapsulation. The die includes a plurality of conductive pads. The conductive vias contacts the conductive pads respectively. The alignment mark is disposed on the die and spaced apart from the conductive vias. The insulating encapsulation encapsulates the die and contacts side surfaces of the conductive vias and the alignment mark.

Abstract: An organic light-emitting diode display including a substrate, a first transistor, and an organic light-emitting element. The first transistor is positioned on the substrate. The first transistor includes a first active layer including a first source region, a first channel region extending from the first source region, a first drain region extending from the first channel region, a first conductive pattern, and a first gate electrode positioned on the first active layer. The organic light-emitting element is connected to the first transistor. The first conductive pattern is in contact with the first active layer and covers the first source region and the second source region.

Abstract: There is provided a technique which includes: forming a film containing at least Si, O and N on a substrate in a process chamber by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: forming a first layer by supplying a precursor gas containing at least a Si—N bond and a Si—Cl bond and a first catalyst gas to the substrate; exhausting the precursor gas and the first catalyst gas in the process chamber through an exhaust system; forming a second layer by supplying an oxidizing gas and a second catalyst gas to the substrate to modify the first layer; and exhausting the oxidizing gas and the second catalyst gas in the process chamber through the exhaust system.

Abstract: Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes providing a semiconductor substrate; forming a plurality of fins on a surface of the semiconductor substrate; forming an isolation flowable layer covering the plurality of fins over the semiconductor substrate; performing a first annealing process to turn the isolation flowable layer into an isolation film; and forming first well regions and second well regions in the fins and the semiconductor substrate. The second well regions are at two sides of the first well regions and contact with the first well regions; the first well regions have a first type of well ions; the second well regions have a second type of well ions; and the first type is opposite to the second type in the conductivities.

Abstract: Methods for forming silicon nitride films are provided. In some embodiments, silicon nitride can be deposited by atomic layer deposition (ALD), such as plasma enhanced ALD. One or more silicon nitride deposition cycle comprise a sequential plasma pretreatment phase in which the substrate is sequentially exposed to a hydrogen plasma and then to a nitrogen plasma in the absence of hydrogen plasma, and a deposition phase in which the substrate is exposed to a silicon precursor. In some embodiments a silicon hydrohalide precursors is used for depositing the silicon nitride. The silicon nitride films may have a high side-wall conformality and in some embodiments the silicon nitride film may be thicker at the bottom of the sidewall than at the top of the sidewall in a trench structure. In gap fill processes, the silicon nitride deposition processes can reduce or eliminate voids and seams.

Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.

Abstract: Some embodiments include methods of forming integrated assemblies. First conductive structures are formed within an insulative support material and are spaced along a first pitch. Upper regions of the first conductive structures are removed to form first openings extending through the insulative support material and over lower regions of the first conductive structures. Outer lateral peripheries of the first openings are lined with spacer material. The spacer material is configured as tubes having second openings extending therethrough to the lower regions of the first conductive structures. Conductive interconnects are formed within the tubes. Second conductive structures are formed over the spacer material and the conductive interconnects. The second conductive structures are spaced along a second pitch, with the second pitch being less than the first pitch. Some embodiments include integrated assemblies.

Abstract: A light emitting diode is provided to comprises: a substrate that has an elongated rectangular shape in one direction; a light emitting structure positioned on the substrate and having an opening for exposing a first conductive semiconductor layer; a first electrode pad disposed to be closer to a first corner of the substrate; a second electrode pad disposed to be relatively closer to a second corner of the substrate opposing to the first corner; a first extension extending from the first electrode pad; and a second extension and a third extension extending from the second electrode pad to sides of the first extension, wherein an imaginary line connecting an end of the second extension and an end of the third extension is located between the first electrode pad and the first corner.

Abstract: A semiconductor device includes a semiconductor layer, a metal layer electrically contacting the semiconductor layer, and a two-dimensional material layer between the semiconductor layer and the metal layer and having a two-dimensional crystal structure.