Abstract: A weather radar with a transmission antenna array that outputs a high aspect ratio FMCW transmission beam that illuminates an area in the field of regard in elevation and may be electronically scanned in azimuth. The weather radar includes a receive array and receive electronics that may receive the reflected return radar signals and electronically form a plurality of receive beams that may be used to determine characteristics of the area in the field of regard. The receive beams may be used to determine reflectivity of weather systems and provide a coherent weather picture. The weather radar may simultaneously process the receive signals into monopulse beams that may be used for accurate navigation as well as detection and tracking of objects, such as birds, aircraft, UAVs and the like.

Abstract: A magnetic recording array includes: a plurality of spin elements each including a wiring and a laminated body having a first ferromagnetic layer laminated on the wiring and arranged in a matrix; a plurality of write wirings connected to first ends of the spin elements' wiring; a plurality of read wirings connected to the laminated bodies of the spin elements; a plurality of common wirings connected to second ends of the wirings of the spin elements belonging to the same column; and a control unit configured to control a write current flowing between first and second ends of each spin element, wherein when data writing is performed continuously, the unit is configured to prohibit writing to at least a spin element connected to the same common wiring as a first spin element and adjacent to the first spin element after the first element to which the current is applied.

Abstract: A semiconductor die includes one or more semiconductor devices (e.g., memory array, processors), first and second banks of I/O ports arranged along one or more sides of the die, and a multiplexing circuit. The multiplexing circuit can be changed between a first state and a second state. In the first state the first bank of I/O ports is coupled to the semiconductor device(s) and the second bank of I/O ports is not coupled to the semiconductor device(s), and in the second state the first bank of I/O ports is not coupled to the semiconductor device(s) and the second bank of I/O ports is coupled to the semiconductor device(s). The state of the multiplexing circuit can be set, for example, by an on-die fuse circuit or an externally accessible select line. The semiconductor die can be included in a chip package, which can be included on a printed circuit board.

Abstract: The present disclosure relates to a system and method of aligning a sensor assembly for a vehicle. The sensor assembly is disposed along a vehicle body and has a sensory face from which a measurement signal is transmitted. The sensor alignment system includes an alignment gauge that measures a datum angle of the sensor assembly, a sensor adjustment tool that adjusts a position of the sensor assembly relative to the vehicle body, and a controller that is in communication with the alignment gauge and the sensor adjustment tool. The controller further operates the sensor adjustment tool to control the datum angle of the sensor assembly to within a tolerance range.

Abstract: Semiconductor packages having nonspherical filler particles are described. In an embodiment, a semiconductor package includes a package substrate having a dielectric layer over an electrical interconnect. The dielectric layer includes nonspherical filler particles in a resin matrix. The nonspherical filler particles have an aspect ratio greater than one.

Abstract: The subject matter discloses a method to determine a relative direction of a target RF transmitter, performed by a direction finding (DF) system comprising at least a pair of antennas having an electromagnetic-absorbing material between them, comprising conducting wireless communication between the target RF transmitter and each one of the antennas of the DF system, measuring the time of flight (TOF) of the target RF transmitter received at each antenna, calculating the difference between the TOFs measured at each one of the antennas in the pair, and determining a relative direction of the target RF transmitter based on the TOF required to reach each of the antennas.

Abstract: An electronic device includes a printed circuit board (PCB) that supports an integrated circuit (IC) chip. The device also includes a lid over the IC chip. A thermal interface material (TIM) is configured to transfer thermal energy from the IC chip to the lid. A heat spreader forms a cavity in communication with the lid. The heat spreader is at least partially filled with a liquid that is configured to change phases during operation of the IC chip.

Abstract: A wavelength conversion module, a method of forming the same and a projection apparatus are provided. The wavelength conversion module includes a substrate and a wavelength conversion layer. The substrate has a rough surface including two first regions and a second region located between the two first regions in a radial direction on the substrate. The wavelength conversion layer is located on the substrate and includes a wavelength conversion material, a bonding material and diffuse reflection particles. The wavelength conversion material is distributed in the bonding material. The diffuse reflection particles are located on the rough surface of the substrate and between the wavelength conversion material and the substrate. A second density of the diffuse reflection particles in the second region is greater than a first density of the same in one of the two first regions.

Abstract: The structure of a semiconductor device with negative capacitance (NC) dielectric structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure with a fin base portion and a fin top portion on a substrate, forming a spacer structure in a first region of the fin top portion, and forming a gate structure on a second region of the fin top portion. The spacer structure includes a first NC dielectric material and the gate structure includes a gate dielectric layer with a second NC dielectric material different from the first NC dielectric material.

Abstract: A method for correlating energy usage data and water usage data to a waste scoring system is described. In one embodiment, the method includes receiving energy usage data and water usage data from a plurality of users, identifying at least one user group from the plurality of users based on predetermined parameters, and calculating average energy usage and average water usage for each of the user groups. The energy usage data and water usage data received for an individual user may then be compared to the calculated average energy usage and calculated average water usage for at least one of the user groups, and a general waste score may be calculated for the individual user. In some cases, a plurality of sub-waste scores may be calculated indicating factors of energy usage and factors of water usage for the individual user.

Abstract: A semiconductor integrated circuit device including a plurality of rows of IO cells has a configuration capable of avoiding a latchup error without causing an increase in area. The device includes a first IO cell row placed closest to an edge of a chip and a second IO cell row placed adjacent to a core region side of the first IO cell row. Each of the IO cells of the first and second IO cell rows has a high power supply voltage region and a low power supply voltage region provided separately in a direction perpendicular to a direction in which the IO cells are lined up. The IO cell rows are placed so that the high power supply voltage regions of these rows are mutually opposed.

Abstract: Techniques and mechanisms for operating transistors that are in a stacked configuration. In an embodiment, an integrated circuit (IC) device includes transistors arranged along a line of direction which is orthogonal to a surface of a semiconductor substrate. A first epitaxial structure and a second epitaxial structure are coupled, respectively, to a first channel structure of a first transistor and a second channel structure of a second transistor. The first epitaxial structure and the second epitaxial structure are at different respective levels relative to the surface of the semiconductor substrate. A dielectric material is disposed between the first epitaxial structure and the second epitaxial structure to facilitate electrical insulation of the channels from each other. In another embodiment, the stacked transistors are coupled to provide a complementary metal-oxide-semiconductor (CMOS) inverter circuit.

Abstract: The present disclosure relates to an array substrate, manufacturing method thereof, and a display panel. The array substrate includes a substrate, at least a first top gate TFT and at least a first bottom gate TFT disposed on the substrate and located in each sub-pixel region; a gate of the first top gate TFT and a gate of the first bottom gate TFT are formed in a same layer with same material, an active layer pattern of the first top gate TFT and an active layer pattern of the first bottom gate TFT are respectively arranged on two sides of the gate, and orthographic projections of the active layer pattern of the first top gate TFT and the active layer pattern of the first bottom gate TFT on the substrate are spaced from each other in a first direction.

Abstract: A field effect transistor includes an exposed channel region disposed between a source region and a drain region. A gate electrode is disposed over the exposed channel region. An electrolyte gel is disposed between the gate electrode and the exposed channel region, wherein ions are immobilized in the electrolyte gel below a transition temperature and mobilized above the transition temperature to increase device resistance.

Abstract: A semiconductor device package includes a first substrate, a dielectric layer, a thin film transistor (TFT) and an electronic component. The first substrate has a first surface and a second surface opposite to the first surface. The dielectric layer is disposed on the first surface of the first substrate. The dielectric layer has a first surface facing away from the first substrate and a second surface opposite to the first surface. The TFT layer is disposed on the dielectric layer. The electronic component is disposed on the second surface of the first substrate. A roughness of the first surface of the dielectric layer is less than a roughness of the first surface of the first substrate.

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.

Abstract: The present technology relates to a solid-state imaging device and an electronic apparatus capable of improving the accuracy of phase difference detection while suppressing degradation of a picked-up image. There is provided a solid-state imaging device including: a pixel array unit, a plurality of pixels being two-dimensionally arranged in the pixel array unit, a plurality of photoelectric conversion devices being formed with respect to one on-chip lens in each of the plurality of pixels, a part of at least one of an inter-pixel separation unit formed between the plurality of pixels and an inter-pixel light blocking unit formed between the plurality of pixels protruding toward a center of the corresponding pixel in a projecting shape to form a projection portion. The present technology is applicable to, for example, a CMOS image sensor including a pixel for detecting the phase difference.

Abstract: A memory structure, and a method for forming the same, includes a spin-orbit-torque electrode within a dielectric layer located above a substrate. The spin-orbit-torque electrode including a first conductive material, and a spin-orbit torque via is directly above the spin-orbit-torque electrode that includes a second conductive material. A magnetic tunnel junction pillar is directly above the spin-orbit torque via, and the spin-orbit-torque via contacting a center of a bottom surface of the magnetic-tunnel-junction pillar. A third conductive material is positioned directly below the bottom surface of the magnetic tunnel junction pillar on opposite sides of the spin-orbit torque via and directly above the spin-orbit-torque electrode. The third conductive material, the spin-orbit torque electrode and the spin-orbit torque via form a bottom spin-orbit torque electrode of the magnetic tunnel junction pillar.

Abstract: A semiconductor device includes a first level having a plurality of transistor devices, and a first wiring level positioned over the first level. The first wiring level includes a plurality of conductive lines extending parallel to the first level, and one or more programmable horizontal bridges extending parallel to the first level. Each of the one or more programmable horizontal bridges electrically connects two respective conductive lines of the plurality of conductive lines in the first wiring level. The one or more programmable horizontal bridges include a programmable material having a modifiable resistivity in that the one or more programmable horizontal bridges change between being conductive and being non-conductive.

Abstract: A system and method for measuring thicknesses of layers of a multi-layered structure. The method includes generating a terahertz wave pulse, transmitting the terahertz wave pulse to a multi-layered structure having multiple layers of materials, receiving reflected terahertz wave pulses reflected by boundaries between the multiple layers as the terahertz wave pulse penetrates the structure, and processing the reflected terahertz wave pulses to: (i) determine whether the reflected terahertz wave pulses have a pulse width overlap; (ii) in response to determining that a pulse width overlap exists, generate modified reflected terahertz wave pulses; measure the time delays associated with each of the modified reflected terahertz pulses and (ii) determine a thickness of each of the multiple layers of materials based upon the time delay and a material refractive index of each of the materials.