Abstract: A method for increasing a forward biased safe operating area of a device includes forming a gate; and forming a segmented source close to the gate, wherein the segmented source includes first segments associated with a first threshold voltage and second segments associated with a second threshold voltage different from the first threshold voltage, wherein at least one device characteristic associated with the first segments is different from the same device characteristic associated with the second segments.

Abstract: A magnetic memory device includes a magnetic tunnel junction pattern on a substrate, a first conductive pattern between the substrate and the magnetic tunnel junction pattern, lower contact plugs between the first conductive pattern and the substrate and disposed at respective sides of the magnetic tunnel junction pattern, and second conductive patterns on the lower contact plugs, respectively. The second conductive patterns connect the lower contact plugs to the first conductive pattern. The second conductive patterns include a ferromagnetic material.

Abstract: Systems, methods, and computer-readable media for receiver channel calibration are provided. The method includes generating a plurality of calibration signals corresponding to a plurality of receiver channels, respectively. The plurality of calibration signals are combined with a plurality of data signals, respectively, thereby generating a plurality of combined signals. The plurality of combined signals are propagated through at least portions of the plurality of receiver channels, respectively. The plurality of calibration signals are extracted from the propagated plurality of combined signals, respectively. At least two signal characteristics of at least two of the extracted plurality of calibration signals are compared. At least one adjustment in gain, phase, or timing for at least one of the receiver channels is identified based on a result of the comparing. Based on the identified adjustment, a data signal received via the at least one of the plurality of receiver channels is adjusted.

Abstract: A method of forming a semiconductor device includes forming a first dummy gate structure and a second dummy gate structure over a fin protruding above a substrate, where the first dummy gate structure and the second dummy gate structure are surrounded by a dielectric layer; and replacing the first dummy gate structure and the second dummy gate structure with a first metal gate and a second metal gate, respectively, where the replacing includes: removing the first and the second dummy gate structures to form a first recess and a second recess in the dielectric layer, respectively; forming a gate dielectric layer in the first recess and in the second recess; forming an N-type work function layer and a capping layer successively over the gate dielectric layer in the second recess but not in the first recess; and filling the first recess and the second recess with an electrically conductive material.

Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. An exemplary semiconductor device comprises a fin disposed over a substrate, wherein the fin includes a channel region and a source/drain region; a gate structure disposed over the substrate and over the channel region of the fin; a source/drain feature epitaxially grown in the source/drain region of the fin, wherein the source/drain feature includes a top epitaxial layer and a lower epitaxial layer formed below the top epitaxial layer, and the lower epitaxial layer includes a wavy top surface; and a contact having a wavy bottom surface matingly engaged with the wavy top surface of the lower epitaxial layer of the source/drain feature.

Abstract: A method of receiving and decoding non-legacy GNSS signals and re-transmitting these in real-time as legacy GPS (L1-C/A) signals decoding into standard PVT/PNT information then re-encoding using a real-time GPS simulator as legacy GPS code signals, and outputting as a legacy GPS antenna signal. A navigational apparatus for performing the method may further include an Inertial Measurement Unit, Inertial Navigation System (IMU/INS) module and oscillator coupled to the GPS simulator for providing an inertial location signal supplementing the GNSS signal to the GPS simulator, wherein the GPS simulator encodes the RF simulated GPS signal based at least in part on the inertial location signal for a period when at least one of the GNSS signal or the PVT/PNT signal is not available.

Abstract: A semiconductor package includes a redistribution structure, a memory wafer, semiconductor dies and conductive vias. The memory wafer, disposed over the redistribution structure, includes at least one memory die. The semiconductor dies are disposed side by side with respect to each other, between the memory wafer and the redistribution structure, and are electrically connected to the redistribution structure. The conductive vias electrically connect the at least one memory die with the redistribution structure. A semiconductor package includes a redistribution structure, a reconstructed wafer, and a heat sink. The reconstructed wafer is disposed on the redistribution structure. The reconstructed wafer includes logic dies and memory dies. The logic dies are electrically connected to the redistribution structure. The memory dies are electrically connected to the redistribution structure and vertically stacked with the logic dies. The heat sink is disposed on the reconstructed wafer.

Abstract: A device is provided. The device includes an interfacial layer on a semiconductor device channel. The device further includes a dipole layer on the interfacial layer, and a gate dielectric layer on the dipole layer. The device further includes a first work function layer associated with a first field effect transistor device; and a second work function layer associated with a second field effect transistor device, such that the first field effect transistor device and second field effect transistor device each have a different threshold voltage than a first field effect transistor device and second field effect transistor device without a dipole layer.

Abstract: In some examples, a radar system includes first direct digital synthesizer (DDS) circuitry and first phase-locked loop (PLL) circuitry configured to generate a first sinusoidal signal based on a first DDS signal generated by the first DDS circuitry. In some examples, the radar system further includes transmitter circuitry configured to generate a radar signal based on the first sinusoidal signal. In some examples, the radar system also includes one or more antennas configured to transmit the radar signal and receive a return signal based on the radar signal. In some examples, the radar system includes second DDS circuitry, second PLL circuitry configured to generate a second sinusoidal signal based on a second DDS signal generated by the second DDS circuitry, and receiver circuitry configured to process the return signal based on the second sinusoidal signal.

Abstract: An LED filament includes an underlying layer exhibiting a first appearance at a first temperature, and an over-coated layer comprising a thermochromic material that exhibits at the first temperature, a preselected appearance other than the first appearance, and at a second temperature, a transparent or translucent appearance.

Abstract: The subject matter discloses a casing of a mobile electronic device, comprising: a body, comprising: two or more antennas for exchanging wireless signals with a target device; an electromagnetic absorbing material located between the two or more antennas; electrical circuitry for sending information concerning the wireless signals exchanged between the two or more antennas and the target device to a direction finding module, wherein the direction finding module is operative to determine a relative direction of the target device based on the wireless signals exchanged between the two or more antennas and the target device.

Abstract: The subject matter discloses a method to determine a relative direction of a target RF transmitter, performed by a direction finding (DF) system comprising at least a pair of antennas having an electromagnetic-absorbing material between them, comprising conducting wireless communication between the target RF transmitter and each one of the antennas of the DF system, measuring the time of flight (TOF) of the target RF transmitter received at each antenna, calculating the difference between the TOFs measured at each one of the antennas in the pair, and determining a relative direction of the target RF transmitter based on the TOF required to reach each of the antennas.

Abstract: Various embodiments may provide a semiconductor package. The semiconductor package may include a substrate including a via hole. The semiconductor package may also include a chip attached to the substrate. The semiconductor package may further include a prefabricated ferromagnetic pin having a first portion held by the via hole, a second portion extending from a first end of the first portion, and a third portion extending from a second end of the first portion opposite the first end. The semiconductor package may also include a first magnetic shield structure attached to or extended from the second portion of the prefabricated ferromagnetic pin. The semiconductor package may further include a second magnetic shield structure attached to or extended from the third portion of the prefabricated ferromagnetic pin, such that at least a portion of the chip is between the first magnetic shield structure and the second magnetic shield structure.

Abstract: A semiconductor device package includes a dielectric layer and a stacking conductive structure. The dielectric layer includes a first surface. The stacking conductive structure is disposed on the first surface of the dielectric layer. The stacking conductive structure includes a first conductive layer disposed on the first surface of the dielectric layer, and a second conductive layer stacked on the first conductive layer. A first surface roughness of the first surface of the dielectric layer is larger than a second surface roughness of a top surface of the first conductive layer, and the second surface roughness of the top surface of the first conductive layer is larger than a third surface roughness of a top surface of the second conductive layer.

Abstract: Described is a monolithic integrated circuit for use in quantum computing based on single and multiple coupled quantum dot electron- and hole-spin qubits monolithically integrated with the mm-wave spin manipulation and readout circuitry in commercial complementary metal-oxide-semiconductor (CMOS) technology. The integrated circuit includes a plurality of n-channel or p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) cascodes each including a single-spin qubit or two coupled quantum dot qubits formed in an undoped semiconductor film adjacent at least one top gate. There is also a back gate formed in a silicon substrate adjacent a buried oxide layer or the at least one top gate, where the back gate controls the electron or hole entanglement and exchange interaction between the two coupled quantum dot qubits. The monolithic integrated circuits described may be used for monolithically integrated semiconductor quantum processors for quantum information processing.

Abstract: A magnetic tunnel junction (MTJ) element includes a free layer, a pinned layer on the free layer, and a dielectric layer extending between the free layer and the pinned layer. A spin orbit torque (SOT) generator is provided, which contacts at least a portion of the free layer. A plane extending between the SOT generator and the free layer intersects a plane extending between the free layer and the dielectric layer. The SOT generator is configured to modulate current that passes between the free layer, the dielectric layer, and the pinned layer. This SOT generator can include a pair of electrodes that are spaced apart from each other in a direction orthogonal to a stacking direction of the free layer, the dielectric layer and the pinned layer. This SOT generator may include a metal selected from a group consisting of Pt, W, and Ta, or may include a topological insulator.

Abstract: A semiconductor device includes a first insulating resin member sealing a mounting surface of a lead frame, and a second insulating resin member sealing a heat dissipating surface. The second insulating resin member contains a filler having a maximum diameter of 0.02 mm to 0.075 mm. The second insulating resin member includes a thin molded portion formed in contact with the heat dissipating surface of the lead frame. The thin molded portion has a thickness 1.1 times to 2 times the maximum diameter of the filler. The semiconductor device includes, at an interface between the first insulating resin member and the second insulating resin member, a mixture layer in which these resins are mixed with each other.

Abstract: In an example, a communication module such as an optoelectronic communication module may include an integrated circuit (IC), an electrical interconnect, and an interposer circuit. The electrical interconnect may include a radio frequency (RF) interconnect or a direct current (DC) interconnect. The interposer circuit may be electrically coupled between the IC and the electrical interconnect.

Abstract: Integrated circuit devices and methods of forming the same are provided. An integrated circuit device in an embodiment includes a first multi-gate active region over a substrate, a second multi-gate active region over the substrate, a first gate structure over the first multi-gate active region, a second gate structure over the second multi-gate active region, and a dielectric feature disposed between the first gate structure and the second gate structure. The dielectric feature includes an oxygen-free layer in contact with the first gate structure and the second gate structure, a silicon oxide layer over the oxygen-free layer, and a transition layer disposed between the oxygen-free layer and the silicon oxide layer. An oxygen content of the transition layer is smaller than an oxygen content of the silicon oxide layer.

Abstract: A power device includes a substrate including a drift layer and having a first region and a second region, the drift layer having impurities of a first type; a switch formed in the first region; a diode formed in the second region; a metal structure formed over a surface of the substrate, the metal structure having a first thickness over the first region of the substrate and a second thickness over the second region of the substrate, the first thickness and second thickness having at least 3 um in thickness difference; and a zone provided in the drift layer in the second region of the substrate, the zone having impurities of a second type that is different from the first type.